---
title: 'Advanced Packaging SI/PI Engineer at Etched'
canonical: 'https://feeny.ai/job/advanced-packaging-si-pi-engineer-etched-san-jose-47he7k0hp901'
type: 'job'
last_seen: '2026-09-07'
---

# Advanced Packaging SI/PI Engineer at Etched

- **Company:** [Etched](https://feeny.ai/companies/etched)
- **Location:** San Jose, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-08-27
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.ashbyhq.com/etched/5c3d84b0-0d6a-430b-80b5-f378eb541202

## Job description

## About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a Signal & Power Integrity Engineer you will be responsible for the electrical performance of our AI accelerator platform across silicon, package, and board. The ideal candidate will have extensive experience with high-power package and board designs, robust power delivery networks, and high-speed signaling solutions in advanced packaging. You will work closely with silicon, package, platform, and system teams to co-design world-class platforms with OSAT and ODM partners. Intense focus on pushing what is possible in power delivery and high-speed signaling for our silicon.

## Key Responsibilities

- SI/PI analysis of designs and optimization within 2D/2.5D/3D packages
- Close interaction with Package Layout Designers, ASIC PD and IP teams as well as Board Schematic/Layout/SI/PI teams to optimize the best electrical performance
- Drive SI requirements into interposer/substrate layout (high-speed routing: 112G/224G) from preliminary design through tape-out.
- Drive PDN design and decoupling strategy across substrate and interposer, owning DC IR drop, dynamic IR drop, and impedance targets across all rails.
- Own ball map / C4 / BGA pin assignment from soft freeze through final freeze in partnership with package layout, ASIC PD, and board layout teams.
- Support board-level SI/PI and rack-level scale-up topology studies, including rack test vehicle design and cable characterization.
- Participating in cross-functional meetings and design reviews.

You may be a good fit if you have (Must-have qualifications)

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a strong understanding of signal integrity and power integrity concepts and fundamentals.
- 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms.
- Proven experience defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis.
- Experience with developing systems with high-speed interfaces like HBM, SerDes and D2D interfaces.
- Hands-on expertise with one or more of: ANSYS HFSS / SIwave, Cadence Sigrity (PowerSI / PowerDC), Keysight ADS.
- Experience with CoWoS or equivalent advanced packaging materials and technologies including interposer SI/PI implications, C4 bump planning, and substrate stack-up trade-offs.
- Track record of designing and correlating SI/PI test vehicles against silicon measurement during bring-up and lab characterization.
- Strong analytical and communication skills, comfortable presenting risk, sign-off status, and trade-offs to cross-functional leadership.
- Deeply creative and able to think from first principles.

Strong candidates may also have experience with (Nice-to-have qualifications)

- Familiarity with full RTL-to-GDSII context and how PD decisions interact with package and board PDN.
- Experience with multi-die, 2.5D, or 3D packaging signoff, including chip-package-system (CPS) co-design.
- Project management experience coordinating across internal teams, OSAT partners, and PCB ODMs.
- Familiarity with modern ML and LLM model architectures, accelerator architectures, or HPC system design.
- Startup experience or comfort working in fast-paced environments.

## Benefits

- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in our office
- Unlimited compute budget subject to ROI justification

## How we’re different

Etched believes in the Bitter Lesson http://www.incompleteideas.net/IncIdeas/BitterLesson.html. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

## About Etched

## Company Overview
- **One-liner**: Etched designs and manufactures specialized ASICs (application-specific integrated circuits) that are hardwired to run transformer-based AI models, offering an order-of-magnitude improvement in inference cost and energy efficiency over general-purpose GPUs.
- **Entity Type**: Private (Series B / later stage; total raised $800M as of June 2026)
- **Headquarters**: San Jose, California, USA (also has offices in Cupertino, CA; Sacramento, CA; and small presence in Taiwan, Canada, UK, Bulgaria)
- **Founded**: 2022
- **Founders**: Gavin Uberti (CEO), Robert Wachen (President & COO), Chris Zhu (Co-Founder)

## Core Business
- **Primary industry**: AI hardware / semiconductor design / computer hardware manufacturing
- **Target customers**: Frontier AI labs, hyperscalers, and enterprises running large-scale transformer inference workloads (B2B, enterprise)
- **Mission / purpose**: Build hardware for superintelligence – specifically, the world’s most powerful servers for transformer inference.

## Products & Services
- **Sohu Chip (ASIC)**: A transformer-specific ASIC manufactured by TSMC. It burns the transformer architecture directly into silicon, eliminating the overhead of general-purpose GPUs for inference.
- **Frontier Inference Clusters**: Full-stack systems that bundle the Sohu chip with custom-designed racks, networking, and software. Customers place orders for complete systems, not just chips. Etched claims they deliver more tokens per dollar and per watt for dense models, sparse MoEs, diffusion models, and more.
- **Software Stack**: Includes compiler and runtime optimizations built by a team with deep experience (former Apache TVM developer, ex-Google TPU software lead).

## Market Standing
- **Valuation**: $5 billion post-money valuation (as of December 2025 / disclosed June 2026)
- **Key Metric**: $1 billion in contract orders (booked) for its systems; total funding of $800M (including an unannounced $500M round closed Dec 2025 led by Stripes)
- **Notable Investors**: Stripes (lead), VentureTech Alliance, Jane Street, Hudson River Trading, Two Sigma, Ribbit Capital. Angel investors include Andrej Karpathy, Geoffrey Hinton, Fei-Fei Li, Arthur Mensch, Scott Wu, Stanley Druckenmiller, Peter Thiel. Earlier backers: Positive Sum, Primary Venture Partners.
- **Growth Signals**:
  - Headcount: 258 employees (as of mid-2026), up 141% year-over-year
  - 100+ active job postings across engineering, operations, and business functions
  - $500M raise in late 2025; first chip manufactured by TSMC in 2025 and now being tested with customers
  - Talent sources include Google (21), Apple (17), NVIDIA (16), Tesla (11), Intel (10), AMD (5)

## Competitive Advantages
- **Transformer-specific architecture**: Unlike GPUs (which are general-purpose), Etched’s chip is hardwired only for transformer operations, enabling drastically lower cost and latency for today’s dominant AI model architecture.
- **Full-stack system play**: By selling entire inference clusters (chip + rack + software), Etched captures more value and delivers a turnkey solution competitive with NVIDIA’s DGX/HGX systems.
- **Deeply experienced leadership**:
  - CEO Gavin Uberti (Harvard math researcher, AI compiler expert, Apache TVM contributor)
  - President Robert Wachen (co-founded Prod AI incubator; Thiel Fellow)
  - VP of Platform (ex-NVIDIA 22 years, built HGX/DGX systems)
  - VP of Software (ex-Google DeepMind, lead TPU v1–v5 software)
  - Chief Architect Saptadeep Pal (former Auradine co-founder, chiplet expert)
  - VP of Hardware Engineering Ajat Hukkoo (ex-Cypress CTO, shipped >$1B revenue products)

## Strategic Focus
- **Scale manufacturing and customer deliveries**: With the first chip successfully fabricated, the company is now testing production systems and aims to fulfill $1B in pre-orders.
- **Expand engineering talent**: Aggressively hiring across silicon design, validation, infrastructure, optics, and software to support volume ramp.
- **Maintain technological lead**: Continue refining the ASIC for future transformer variants and MoE mixtures while building out a partner ecosystem.

## Why Work Here
- **Mission-driven, high-impact engineering**: “Building the hardware for superintelligence” – the company is solving one of the hardest problems in compute (inference efficiency) with a focused team.
- **Top-tier team and learning environment**: Colleagues from Google, NVIDIA, Apple, Tesla, Broadcom, and Intel; exposure to full-stack chip-to-system design.
- **In-office culture**: All roles are in-office (Cupertino and San Jose, CA). The company emphasizes on-site collaboration for hardware development. Notable perks are not heavily advertised, but compensation is competitive for the AI hardware space (equity-heavy).
- **Growth trajectory**: 141% headcount growth YoY, hundreds of open roles, and a $5B valuation signal strong backing and career acceleration potential.
- **Intellectual challenge**: Work on chip simulation, RTL design, system validation, or software infrastructure for cutting-edge AI inference.

## Sources
1. [etched.com/careers](https://www.etched.com/careers)
2. [builtin.com/company/etched](https://builtin.com/company/etched)
3. [linkedin.com/company/etched-ai](https://www.linkedin.com/company/etched-ai)
4. [cbinsights.com/company/etched](https://www.cbinsights.com/company/etched)
5. [techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/](https://techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/)

## Other roles at Etched

- [EE Hardware System Engineer (TW)](https://feeny.ai/job/ee-hardware-system-engineer-tw-etched-taipei-fgncym9kzy6w) — Taipei, Taiwan
- [Silicon Validation Engineer, Software](https://feeny.ai/job/silicon-validation-engineer-software-etched-san-jose-qhp3k9xqy5vr) — San Jose, CA
- [RMA & Repair Lead](https://feeny.ai/job/rma-repair-lead-etched-san-jose-q0tmchh0yyrj) — San Jose, CA
- [Substrate IC Package Layout Design Engineer](https://feeny.ai/job/substrate-ic-package-layout-design-engineer-etched-san-jose-g36wmxc8ww9r) — San Jose, CA
- [ECAD Librarian](https://feeny.ai/job/ecad-librarian-etched-san-jose-0h5kvj2cxzk4) — San Jose, CA
- [Inventory Warehouse Coordinator](https://feeny.ai/job/inventory-warehouse-coordinator-etched-san-jose-49b0bs49ce57) — San Jose, CA
- [Logistics Analyst (Taiwan)](https://feeny.ai/job/logistics-analyst-taiwan-etched-taipei-5xzc094cqgzn) — Taipei, Taiwan
- [Communications](https://feeny.ai/job/communications-etched-san-jose-3f4bdr97hysp) — San Jose, CA
- [Production Finance](https://feeny.ai/job/production-finance-etched-san-jose-qfypbv9eh0ws) — San Jose, CA
- [CNC Machinist](https://feeny.ai/job/cnc-machinist-etched-san-jose-vxam0y7m1yc8) — San Jose, CA