---
title: 'AI Silicon, Junior Digital Design Engineer at Unconventional, Inc.'
canonical: 'https://feeny.ai/job/ai-silicon-junior-digital-design-engineer-unconventional-inc-mountain-view-sz9k072xz7hm'
type: 'job'
last_seen: '2026-09-15'
---

# AI Silicon, Junior Digital Design Engineer at Unconventional, Inc.

- **Company:** Unconventional, Inc.
- **Location:** Mountain View, CA
- **Posted:** 2026-06-24
- **Last confirmed live:** 2026-09-15
- **Apply:** https://unconv.ai/careers/?gh_jid=4164485009

## Job description

Junior Member of Technical Staff - AI Silicon Digital Design Engineer

## About Unconventional

Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation - a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale.

At Unconventional, our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient. We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction.

## The Role

As a Member of Technical Staff, SOC Design Engineer, you will be a foundational member of our small, multi-disciplinary R&D team. We are looking for accomplished and highly motivated individuals with a strong understanding of SOC design who are excited to tackle the hardest, most ambiguous technical challenges at the intersection of AI, physics, and computer architecture. You will be responsible for driving invention, prototyping, and validation of the core components of our novel computing platform.

## Responsibilities

- SoC Design & Integration:
- Contribute to the micro-architecture definition and integration of digital blocks, including CPU, interfaces and memory subsystems.
- Assist in the integration of third-party IP into the main SoC fabric.
- Hands-on RTL Implementation:
- Write clean, synthesizable, and high-performance Verilog/SystemVerilog code.
- Perform hands-on RTL design for SoC blocks and digital interfaces, focusing on meeting power, performance, and area (PPA) targets.
- Implement and debug key digital interfaces to ensure system stability.
- Implement advanced techniques for low-power design (clock gating, power domains)
- Synthesis & Timing:
- Perform initial synthesis and formal verification (LEC) to ensure the design is routable and meets frequency targets.
- Create block-level timing constraints
- Lint & CDC: Run and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks using industry standard tools.
- Design Verification (DV) Support:
- Participate in the block-level verification plan and help develop a robust verification environment.
- Triage and debug simulation failures to ensure functional correctness.
- External Coordination:
- Support created technical interfaces, and assist in the hand-off between internal design and physical implementation teams.

## Minimum Qualifications

- Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- Experience: 4+ years of industry experience in digital ASIC/SoC design
- Strong Technical Expertise:
- Expertise in Verilog RTL coding and digital design fundamentals.
- Design Flow Proficiency:
- Familiarity with standard EDA tools for simulation, assertions, synthesis, linting, and clock domain crossing (CDC) analysis
- Understanding of the full ASIC design flow, from specification to tape-out.
- Communication: Excellent written and verbal communication skills

## Preferred Qualifications (Nice to Have)

- Experience with design constraints or architectures related to Machine Learning/Neural Network accelerators is a strong plus.
- Experience with UVM (Universal Verification Methodology) environments for basic debugging.
- Knowledge of formal verification techniques.
- Exposure to post-silicon bring-up and lab debugging using logic analyzers or oscilloscopes.
- Experience with modern design methods, including generative AI code development platforms.
- Experience integrating large analog mixed-signal blocks into larger subsystems.

Why Join Us?

- The Mission: Tackle a fundamental problem that could redefine computing for the next 50 years.
- The Impact: Be a foundational member of a world-class team with an outsized opportunity for ownership and impact.
- The Challenge: Work on deeply challenging, intellectually stimulating problems that sit at the cutting edge of multiple fields.
- The Perks: A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Palo Alto office.

## About Unconventional, Inc.

## Company Overview
- **One-liner**: Unconventional AI is rethinking the foundations of a computer to optimize energy efficiency for AI by building analog chips that run neural networks directly on physics rather than simulating digital logic.
- **Entity Type**: Private (Seed stage – raised $475M seed round)
- **Headquarters**: San Diego, California, United States (also has an office in San Francisco)
- **Founded**: Not explicitly stated; assumed ~2024/2025 based on funding announcement in December 2025
- **Founders**: Naveen Rao (CEO), Michael Carbin (co-founder), Sara Achour (co-founder), Meelan Lee (engineering leader)

## Core Business
- Primary industry/industries: Hardware design for artificial intelligence, analog computing, energy-efficient semiconductors
- Target customers: AI labs, hyperscalers, and enterprises that train and deploy large neural networks (B2B/Enterprise)
- Mission or purpose statement: *“Bringing biology-scale efficiency to artificial intelligence”* – building the right isomorphism for intelligence to unlock efficiency gains far beyond digital simulation

## Products & Services
- **Unconventional AI Chip Platform (in development)**: A novel analog/mixed-signal chip designed specifically for probabilistic AI workloads. The chip stores exact probability distributions in the physical substrate (silicon) rather than using numerical approximations, potentially achieving ~1,000x lower power consumption than digital computers. It is a **Hardware** product, supported by extreme codesign of algorithms and software.

## Market Standing
- **Valuation/Market Cap**: $4.5 billion (as of December 2025 – seed round valuation)
- **Key Metric**: Total Funding $475 million (seed round, December 2025)
- **Notable Investors/Partners**: Lightspeed Venture Partners (co-lead), Andreessen Horowitz (co-lead), Sequoia, Lux Capital, DCVC, Future Ventures, Jeff Bezos (individual), and others. CEO Naveen Rao personally invested $10 million.
- **Growth Signals**: 
  - Named to 2026 CB Insights AI 100 list
  - Headcount of 23 employees with +10.8% monthly growth
  - Monthly website traffic 27,433 (+21.7% growth)
  - Highly active on LinkedIn with 9,516 followers and frequent technical blog posts
  - Launched the “Unconventional Grant” program – $500,000 in funding for bold research ideas in AI compute

## Competitive Advantages
- **First-principles approach**: Rejects digital abstraction for analog/physics-based computation, achieving orders-of-magnitude energy efficiency improvements that conventional GPU architectures cannot match.
- **Extreme codesign**: Hardware, software, algorithms, and models are co-optimized from day one, not adapted from legacy computing paradigms.
- **World-class team**: CEO Naveen Rao (prior exits: Nervana→Intel, Mosaic→Databricks) plus co-founders with deep expertise in AI systems, analog circuits, computing theory, and neuroscience.
- **Massive financial backing**: $475M seed round at a $4.5B valuation provides a long runway for ambitious R&D.

## Strategic Focus
- **Near-term priorities**: Design and tape-out of analog AI chips; recruit top interdisciplinary talent across hardware, software, algorithms, and neuroscience.
- **Long-term direction**: Achieve “biology-scale” energy efficiency (on the order of 20W for human-level intelligence) and scale to meet projected global AI compute demand that could outstrip energy supply within 3–4 years.
- **Research investment**: Active grant program and open collaboration with academic/unconventional thinkers.

## Why Work Here
- **Culture**: Deeply interdisciplinary, first-principles culture that challenges assumptions – described as “endlessly curious, comfortable with discomfort, and drawn to the edge of chaos.”
- **Growth opportunity**: Very early-stage (only 23 employees) with massive ambition; employees can shape foundational technology from the ground up.
- **Remote/Hybrid**: Two offices (San Diego HQ and San Francisco); likely hybrid or on-site given hardware work, but not explicitly stated.
- **Perks & environment**: Small team, high ownership, access to top investors and mentors, and the chance to solve one of AI’s most critical bottlenecks (energy).
- **Talent sources**: Employees come from Databricks, MIT, Cohere, and other top AI/tech organizations – strong peer group.

## Sources
1. [unconv.ai](https://unconv.ai/)
2. [unconv.ai/careers](https://unconv.ai/careers/)
3. [unconv.ai/blog](https://unconv.ai/blog/introducing-unconventional-ai/)
4. [linkedin.com](https://www.linkedin.com/company/unconvai)
5. [a16z.com](https://a16z.com/announcement/investing-in-unconventional/)

## Other roles at Unconventional, Inc.

- [Member of Technical Staff - AI Training Platform](https://feeny.ai/job/member-of-technical-staff-ai-training-platform-unconventional-inc-mountain-view-d1g7x3es47d9) — Mountain View, CA / Seattle, WA
- [Finance Manager, Accounting & FP&A](https://feeny.ai/job/finance-manager-accounting-fp-a-unconventional-inc-mountain-view-s7qznaybwxbd) — Mountain View, CA
- [Member of Technical Staff - Development Experience](https://feeny.ai/job/member-of-technical-staff-development-experience-unconventional-inc-mountain-sb1ydxb6g5rk) — Mountain View, CA / Seattle, WA
- [Member of Technical Staff - Agentic Applications](https://feeny.ai/job/member-of-technical-staff-agentic-applications-unconventional-inc-mountain-view-d5s7z32mqy23) — Mountain View, CA / Seattle, WA
- [AI Systems, Model Optimization](https://feeny.ai/job/ai-systems-model-optimization-unconventional-inc-mountain-view-ca-i-bhb7nvk4vwfb) — Mountain View CA I, United States
- [AI Theory & Systems, Algorithms & Models](https://feeny.ai/job/ai-theory-systems-algorithms-models-unconventional-inc-mountain-view-f0vwf70pgvkv) — Mountain View, CA
- [AI Silicon, Silicon Validation Engineer](https://feeny.ai/job/ai-silicon-silicon-validation-engineer-unconventional-inc-mountain-view-bnzvp2npndhw) — Mountain View, CA
- [AI Silicon, Digital Design Engineer](https://feeny.ai/job/ai-silicon-digital-design-engineer-unconventional-inc-mountain-view-7nbkzmsh4caz) — Mountain View, CA
- [AI Systems, Language & Reasoning Models](https://feeny.ai/job/ai-systems-language-reasoning-models-unconventional-inc-mountain-view-ca-i-ak7pqwr2gn32) — Mountain View CA I, United States
- [AI Silicon, Design Verification](https://feeny.ai/job/ai-silicon-design-verification-unconventional-inc-mountain-view-93xaam2wwy1b) — Mountain View, CA