---
title: 'AI Silicon, Physical Design Engineer at Unconventional, Inc.'
canonical: 'https://feeny.ai/job/ai-silicon-physical-design-engineer-unconventional-inc-mountain-view-arrvvxe2d4vb'
type: 'job'
last_seen: '2026-11-03'
---

# AI Silicon, Physical Design Engineer at Unconventional, Inc.

- **Company:** Unconventional, Inc.
- **Location:** Mountain View, CA
- **Work type:** remote
- **Posted:** 2026-10-01
- **Last confirmed live:** 2026-11-03
- **Apply:** https://unconv.ai/careers/?gh_jid=4420542009

## Job description

## About Unconventional

Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation—a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale.

At Unconventional, our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient. We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction.

## The Role

As a Member of Technical Staff, Physical Design Engineer, you will be a foundational member of our multi-disciplinary R&D team. We are looking for individuals who thrive at the intersection of architecture and silicon, turning novel AI concepts into high-performance, energy-efficient hardware.

You will be responsible for the "back-end" realization of our novel computing platform, taking complex digital logic from RTL to GDSII.

## Responsibilities

- Full RTL-to-GDSII Ownership: Lead the physical implementation of complex, high-performance blocks and top-level SoC integration. This includes floorplanning, power grid design, placement, clock tree synthesis (CTS), routing, and physical verification.
- PPA Optimization: Drive aggressive Power, Performance, and Area (PPA) targets. You will work closely with architects to influence the micro-architecture for better physical routability and timing closure.
- Sign-off & Verification: Own the final sign-off process, including Static Timing Analysis (STA), IR drop analysis (static and dynamic), Electromigration (EM), and Physical Verification (DRC/LVS/ERC).
- Methodology Development: Contribute to the development and automation of our physical design flow. Set best practices for synthesis, formal verification (LEC), and parasitic extraction to ensure first-pass silicon success.
- Cross-Functional Collaboration: Work at the interface of digital and analog design, facilitating the integration of custom analog mixed-signal blocks into the digital fabric.
- Partner Engagement: Work to evaluate potential partners that offer AI tools that could greatly improve chip design efficiency

## Minimum Qualifications

- Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- Experience: 10+ years of industry experience in digital physical design, with a track record of successful tapeouts on modern process nodes (7nm, 5nm, or newer preferred).
- Technical Expertise:
- Expertise in Static Timing Analysis (STA) and timing closure for high-frequency, complex designs.
- Deep understanding of physical design challenges in advanced nodes (multi-patterning, finFET effects, low-voltage operation).
- Proficiency in power integrity analysis and noise coupling mitigation.
- Design Flow Proficiency:
- Expert-level mastery of standard EDA tool suites (e.g., Synopsys Fusion Compiler/IC Compiler II or Cadence Innovus).
- Strong scripting skills in Tcl, Python, or Perl to automate design flows and data analysis.
- Communication: Excellent written and verbal communication skills, with experience managing deliverables from external vendors or design houses.

## Preferred Qualifications (Nice to Have)

- Custom AI Hardware: Experience with physical design for Machine Learning accelerators or large-scale systolic arrays.
- Mixed-Signal Integration: Experience with top-level integration of large, custom analog macros and complex power-sequencing requirements.
- Low Power Design: Hands-on experience with multi-voltage domains, UPF/CPF flows, and advanced power-gating techniques.
- AI Tools: Familiarity with state of the art AI tools to accelerate chip design.

Why Join Us?

- The Mission: Redefine computing for the next 50 years by solving the fundamental energy limitation of AI at a global scale.
- The Impact: Shape the company's future as a foundational team member. Enjoy massive ownership and an outsized opportunity to drive change.
- The Challenge: Dive into deeply complex, intellectually stimulating, and unsolved problems at the cutting edge of multiple, converging fields.
- The Perks: A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Mountain View office.

## About Unconventional, Inc.

## Company Overview
- **One-liner**: Unconventional AI is rethinking the foundations of a computer to optimize energy efficiency for AI by building analog chips that run neural networks directly on physics rather than simulating digital logic.
- **Entity Type**: Private (Seed stage – raised $475M seed round)
- **Headquarters**: San Diego, California, United States (also has an office in San Francisco)
- **Founded**: Not explicitly stated; assumed ~2024/2025 based on funding announcement in December 2025
- **Founders**: Naveen Rao (CEO), Michael Carbin (co-founder), Sara Achour (co-founder), Meelan Lee (engineering leader)

## Core Business
- Primary industry/industries: Hardware design for artificial intelligence, analog computing, energy-efficient semiconductors
- Target customers: AI labs, hyperscalers, and enterprises that train and deploy large neural networks (B2B/Enterprise)
- Mission or purpose statement: *“Bringing biology-scale efficiency to artificial intelligence”* – building the right isomorphism for intelligence to unlock efficiency gains far beyond digital simulation

## Products & Services
- **Unconventional AI Chip Platform (in development)**: A novel analog/mixed-signal chip designed specifically for probabilistic AI workloads. The chip stores exact probability distributions in the physical substrate (silicon) rather than using numerical approximations, potentially achieving ~1,000x lower power consumption than digital computers. It is a **Hardware** product, supported by extreme codesign of algorithms and software.

## Market Standing
- **Valuation/Market Cap**: $4.5 billion (as of December 2025 – seed round valuation)
- **Key Metric**: Total Funding $475 million (seed round, December 2025)
- **Notable Investors/Partners**: Lightspeed Venture Partners (co-lead), Andreessen Horowitz (co-lead), Sequoia, Lux Capital, DCVC, Future Ventures, Jeff Bezos (individual), and others. CEO Naveen Rao personally invested $10 million.
- **Growth Signals**: 
  - Named to 2026 CB Insights AI 100 list
  - Headcount of 23 employees with +10.8% monthly growth
  - Monthly website traffic 27,433 (+21.7% growth)
  - Highly active on LinkedIn with 9,516 followers and frequent technical blog posts
  - Launched the “Unconventional Grant” program – $500,000 in funding for bold research ideas in AI compute

## Competitive Advantages
- **First-principles approach**: Rejects digital abstraction for analog/physics-based computation, achieving orders-of-magnitude energy efficiency improvements that conventional GPU architectures cannot match.
- **Extreme codesign**: Hardware, software, algorithms, and models are co-optimized from day one, not adapted from legacy computing paradigms.
- **World-class team**: CEO Naveen Rao (prior exits: Nervana→Intel, Mosaic→Databricks) plus co-founders with deep expertise in AI systems, analog circuits, computing theory, and neuroscience.
- **Massive financial backing**: $475M seed round at a $4.5B valuation provides a long runway for ambitious R&D.

## Strategic Focus
- **Near-term priorities**: Design and tape-out of analog AI chips; recruit top interdisciplinary talent across hardware, software, algorithms, and neuroscience.
- **Long-term direction**: Achieve “biology-scale” energy efficiency (on the order of 20W for human-level intelligence) and scale to meet projected global AI compute demand that could outstrip energy supply within 3–4 years.
- **Research investment**: Active grant program and open collaboration with academic/unconventional thinkers.

## Why Work Here
- **Culture**: Deeply interdisciplinary, first-principles culture that challenges assumptions – described as “endlessly curious, comfortable with discomfort, and drawn to the edge of chaos.”
- **Growth opportunity**: Very early-stage (only 23 employees) with massive ambition; employees can shape foundational technology from the ground up.
- **Remote/Hybrid**: Two offices (San Diego HQ and San Francisco); likely hybrid or on-site given hardware work, but not explicitly stated.
- **Perks & environment**: Small team, high ownership, access to top investors and mentors, and the chance to solve one of AI’s most critical bottlenecks (energy).
- **Talent sources**: Employees come from Databricks, MIT, Cohere, and other top AI/tech organizations – strong peer group.

## Sources
1. [unconv.ai](https://unconv.ai/)
2. [unconv.ai/careers](https://unconv.ai/careers/)
3. [unconv.ai/blog](https://unconv.ai/blog/introducing-unconventional-ai/)
4. [linkedin.com](https://www.linkedin.com/company/unconvai)
5. [a16z.com](https://a16z.com/announcement/investing-in-unconventional/)

## Other roles at Unconventional, Inc.

- [Technical Recruiter](https://feeny.ai/job/technical-recruiter-unconventional-inc-mountain-view-ezqzga3g25cc) — Mountain View, CA / United States
- [Recruiting Coordinator](https://feeny.ai/job/recruiting-coordinator-unconventional-inc-mountain-view-q9sqk8rvts3r) — Mountain View, CA / United States
- [Technical Program Manager](https://feeny.ai/job/technical-program-manager-unconventional-inc-mountain-view-tma3gr8xy3pf) — Mountain View, CA
- [Member of Technical Staff - Cloud Infrastructure](https://feeny.ai/job/member-of-technical-staff-cloud-infrastructure-unconventional-inc-mountain-view-k7c9dw2qrbp5) — Mountain View, CA / Greater Seattle Area
- [AI Silicon, Analog CAD Engineer](https://feeny.ai/job/ai-silicon-analog-cad-engineer-unconventional-inc-mountain-view-xv268aq0rz6r) — Mountain View, CA
- [AI Silicon, DFT Engineer](https://feeny.ai/job/ai-silicon-dft-engineer-unconventional-inc-mountain-view-qhkz4bax0ygs) — Mountain View, CA
- [Member of Technical Staff - AI Training Platform](https://feeny.ai/job/member-of-technical-staff-ai-training-platform-unconventional-inc-mountain-view-d1g7x3es47d9) — Mountain View, CA / Greater Seattle Area
- [AI Systems, Model Optimization](https://feeny.ai/job/ai-systems-model-optimization-unconventional-inc-mountain-view-ca-i-bhb7nvk4vwfb) — Mountain View CA I, United States
- [AI Theory & Systems, Algorithms & Models](https://feeny.ai/job/ai-theory-systems-algorithms-models-unconventional-inc-mountain-view-f0vwf70pgvkv) — Mountain View, CA
- [AI Silicon, Silicon Validation Engineer](https://feeny.ai/job/ai-silicon-silicon-validation-engineer-unconventional-inc-mountain-view-bnzvp2npndhw) — Mountain View, CA