---
title: 'Analog Layout Lead at Lumilens'
canonical: 'https://feeny.ai/job/analog-layout-lead-lumilens-san-jose-5fmv4e96vhpt'
type: 'job'
last_seen: '2026-09-07'
---

# Analog Layout Lead at Lumilens

- **Company:** Lumilens
- **Location:** San Jose, CA
- **Employment:** full-time
- **Posted:** 2026-09-02
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.ashbyhq.com/lumilens/03bcfd8c-c756-47c3-a2cb-140ce0d55515

## Job description

## ABOUT LUMILENS

At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.

We’re a well-funded startup backed by Mayfield and led by industry’s veterans who’ve built and scaled some of the most transformative technologies in the industry. This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.

If you're looking for mission, momentum, and the chance to make an outsized impact jump on the rocket ship. We’re just getting started.

## POSITION OVERVIEW

We are seeking an Analog Layout Lead to drive full-custom analog and mixed-signal layout for Lumilens’ next-generation silicon platforms. This role will lead complex physical implementation across advanced CMOS nodes, partner closely with circuit design and physical design teams, and establish layout methodologies that ensure performance, reliability, manufacturability, and tape-out readiness across multiple silicon programs.

What You'll Do:

- Lead full-custom layout of complex analog and mixed-signal blocks, including PLLs, ADCs, DACs, LDOs, bandgaps, and high-speed I/O for custom silicon platforms.
- Define and enforce analog layout methodologies, design rules, and best practices across the physical design team.
- Drive parasitic-aware layout strategies to meet stringent noise, matching, signal integrity, and power requirements for mixed-signal designs.
- Collaborate with circuit designers to translate schematic intent into optimized physical implementations, iterating on layout-versus-schematic and parasitic extraction results.
- Own physical verification closure, including DRC, LVS, antenna checks, and sign-off readiness across advanced process nodes.
- Establish floorplanning and integration strategies for analog IP blocks within larger mixed-signal SoC contexts.
- Provide technical guidance and layout direction to engineers and contractors, reviewing layouts and driving consistency in methodology, quality, and schedule execution.
- Partner with process technology and design kit teams to evaluate new process nodes, contribute to PDK qualification, and resolve layout-induced performance issues through post-layout simulation analysis.
- Own long-term physical design roadmaps and methodology investments that scale across multiple silicon programs.

Key Qualifications:

- Bachelor’s degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience.
- 8+ years of experience in full-custom analog and mixed-signal layout for production silicon in advanced CMOS process nodes, preferably 28nm or below.
- 8+ years of hands-on experience with industry-standard layout tools such as Cadence Virtuoso for schematic-driven layout, parasitic extraction, and physical verification.
- Experience leading layout of high-performance analog blocks such as PLLs, voltage regulators, data converters, or high-speed interfaces from concept through tape-out.
- Experience defining and implementing layout methodologies for matching, shielding, noise isolation, and signal integrity in mixed-signal environments.
- Experience collaborating with circuit design teams to interpret simulation requirements and translate them into layout constraints, implementation decisions, and verification closure.
- Experience managing, mentoring, and reviewing the work of layout engineers while coordinating deliverables with external contractors.

Preferred Skills:

- Familiarity with post-layout simulation flows, including RC extraction and back-annotated verification using tools such as Spectre or Calibre.
- Experience contributing to or evaluating process design kits and design rule documentation for new process node bring-up.
- Experience with analog layout for photonics, AI infrastructure, consumer wearable, mobile, or IoT SoCs where power, area, and reliability constraints are critical.
- Experience with 3D stacking technologies, advanced packaging layout considerations, or reusable analog layout templates that improve team-wide efficiency and consistency.

Why Join Us?

● Competitive salary commensurate with experience

● Comprehensive benefits package including health insurance

● Professional development opportunities and certification support

● Access to cutting-edge technology and cloud platforms

● Collaborative work environment with cross-functional teams

● Innovate with a Silicon Valley headquartered team, change the world

● Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender, identity, orientation, veteran status, disability, or any other legally protected status.

## About Lumilens

## Company Overview
- **One-liner**: Lumilens designs and manufactures next-generation photonic interconnects to massively scale AI compute infrastructure.
- **Entity Type**: Private (Series B – led by Accton Technology; prior Series A of $30M from Mayfield and Spark Capital)
- **Headquarters**: San Jose, California, USA
- **Founded**: 2024
- **Founders**: Ankur Singla (CEO), Samuel Liu (VP Products), Ritesh Kapahi (VP/GM India), Dave Friedman (VP Operations)

## Core Business
- **Primary industry**: Photonics / optical interconnects for AI data centers
- **Target customers**: Large-scale AI providers and hyperscale data center operators (B2B, Enterprise)
- **Mission**: “To rapidly innovate in photonics and connectivity architectures to enable the massive scaling of compute infrastructure required to deliver the full potential of AI.”

## Products & Services
- **Photonic Interconnects (Scale-Out & Scale-Up)**: High-density, low-latency optical links that enable cluster-to-cluster and direct GPU-to-GPU connectivity. Supports 100x higher quantity of GPU direct connections than legacy approaches.
  - *Type*: Hardware (silicon photonics modules) + integrated manufacturing
- **Automated Manufacturing Platform**: End-to-end custom robotics and AI-optimized production processes to maximize yield, quality, and supply-chain flexibility.
  - *Type*: Service / Manufacturing capability (in-house)

## Market Standing
- **Valuation/Market Cap**: Not publicly available
- **Key Metric**: Total funding – $30M Series A (June 2024); Series B led by Accton Technology (amount undisclosed)
- **Notable Investors/Partners**: Mayfield, Spark Capital, Accton Technology
- **Growth Signals**:
  - Headcount grew 287% YoY (54 employees as of mid-2025) [linkedin.com]
  - Operations in 8 countries: USA, India, Thailand, Poland, Singapore, Czechia, South Korea, Malaysia
  - 48 active job postings (+23.1% monthly growth) [linkedin.com]
  - Leadership team with deep photonics/networking experience from Cisco, Juniper, Meta, Lumentum, Coherent

## Competitive Advantages
- **In-house silicon photonics development** – full control over design and supply chain
- **Systems-level expertise** – can partner on both scale-out and scale-up architectures
- **Manufacturing automation** – robotics + AI processes enable faster innovation, higher quality, and predictable deployment
- **Standards-based interconnects** – easy deployment into existing infrastructure
- **Manufacturing anywhere** – supply-chain continuity and scalable manufacturing

## Strategic Focus
- Enable massive scaling of AI infrastructure by overcoming electrical/copper limitations with advanced photonics
- Disaggregate GPUs to mitigate power and density challenges in data centers
- Expand manufacturing capacity globally and continue to automate production
- Align product roadmap with industry standards to accelerate adoption

## Why Work Here
- **Culture**: Fast-paced startup environment with deep technical expertise; mission-driven focus on enabling the future of AI
- **Work policy**: In-office (HQ San Jose, CA with Bengaluru, India as major hub) [builtin.com]
- **Perks**: Opportunity to work on cutting-edge photonics, robotics, and AI manufacturing; direct impact on world’s largest AI infrastructure
- **Engineering culture**: Heavy emphasis on silicon photonics, hardware design, robotics automation, and system-level architecture. Teams are led by veterans from Cisco, Juniper, Meta, Lumentum, Coherent.

## Sources
1. [lumilens.com](https://lumilens.com/) – Company overview, mission, leadership, products
2. [lumilens.com/company](https://lumilens.com/company) – Vision, investors, leadership team
3. [builtin.com](https://builtin.com/company/lumilens) – Career page, employee count, year founded, office policy
4. [linkedin.com](https://www.linkedin.com/company/lumilens) – Headcount, funding details, geographic/department breakdown, job trends, talent sources
5. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/lumilens) – Current job openings (48 listings)

## Other roles at Lumilens

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- [Optical Transceiver Product Engineer](https://feeny.ai/job/optical-transceiver-product-engineer-lumilens-thailand-f5tgy64vcaxr) — Thailand
- [Product Quality Engineer](https://feeny.ai/job/product-quality-engineer-lumilens-chon-buri-45vb6wx9tam7) — Chon Buri, Thailand
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- [IT Specialist Intern](https://feeny.ai/job/it-specialist-intern-lumilens-san-jose-psmknddggbz7) — San Jose, CA
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