--- title: 'Architecture - I/O Architect at Eliyan' canonical: 'https://feeny.ai/job/architecture-i-o-architect-eliyan-bay-area-9redkrjbdzh7' type: 'job' last_seen: '2026-09-07' --- # Architecture - I/O Architect at Eliyan - **Company:** Eliyan - **Location:** Bay Area - **Employment:** full-time - **Work type:** onsite - **Posted:** 2025-09-29 - **Last confirmed live:** 2026-09-07 - **Apply:** https://jobs.lever.co/eliyan/685da76d-55f6-43b2-9ecb-c3c34a4c5e39 ## Job description Join the leading chiplet startup! As an Eliyan NuLink PHY IO Architect, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the definition and development of cutting-edge ASICs from RTL to GDSII.  You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will own the architecture, oversee design and validation, and be a focal point for customer and marketing team interactions. You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits. ONSITE M-F Key Responsibilities: - Architecture: Define NuLink PHY subsystems (physical and logical/link layers) and hierarchical modular protocol bridges between PCIe, AXI4, APB, CHI, CXL (.io/.cache/.mem), DDR to name a few. Definition of a firmware first based hardware architecture approach. - Protocol Design: Design protocol conversion layers with transaction ordering, credit-based flow control, QoS, address translation, coherency management, and memory semantics across protocol domains - Performance Evaluation and Optimization: Model and tune PHY data path, link protocols, and CDC architectures for protocol efficiency, bandwidth, latency, power, and signal integrity.  Conduct technical evaluation and benchmark analysis against internal and external IPs. - Collaboration: Partner with ASIC, firmware, and post-silicon teams. Support customer integration for compute-to-memory (CXL/DDR), processor interconnect (AXI/PCIe), and control plane (APB).  Create clear and comprehensive architecture specifications with foolproof integration guidelines. - Validation: Review characterization plans for PLL, VCO, ATB, and link training. Create protocol testbenches validating transaction handling, latency, throughput, and compliance - Compliance: Ensure UCIe, PCIe, CXL, AMBA AXI/APB, and DDR specification compliance. Define interoperability requirements and protocol error handling. Be part of industry standards bodies and work groups to keep Eliyan's product implementations up to date with the latest versions of the standards. - Leadership: Mentor engineers on protocol implementation, timing constraints, and hierarchical design.  Effectively collaborate with industry technologists, business leaders and ability to network seamlessly with industry peers to influence stakeholders. Minimum Qualifications: - Expertise in multiple areas of architecture definition, chip micro-architecture, protocol definition and implementation - Strong knowledge of two or more of the following connectivity protocols - PCIe, UCIe, UALink, Ethernet, DDR, AMBA - Strong scripting and automation skills - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field - 8+ years' of experience Ideal Qualifications: - 15+ years of experience in ASIC architecture with strong bias for practical logic design and influence of physical implementation, with a proven track record of leading teams through successful tapeouts - Performance modeling of hardware implementations with high level languages like C, C++ or SystemC - Adept at clocking and floorplan guidelines for PHY implementation - Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve productivity and power aware designs - Exceptional problem-solving skills. ## About Eliyan ## Company Overview - **One-liner**: Eliyan develops high-bandwidth, low-power chiplet interconnect technology (NuLink) that solves data bottlenecks in AI and data center chips. - **Entity Type**: Private (Series C-II) - **Headquarters**: Santa Clara, California, United States - **Founded**: 2021 - **Founders**: Ramin Farjadrad (CEO), Syrus Ziai (VP Engineering), Patrick Soheili (Chief Strategy & Business Officer) ## Core Business - Primary industry: Semiconductor Manufacturing (chiplet interconnect IP and PHY silicon) - Target customers: B2B – companies building custom AI chips (hyperscalers, chip designers, networking firms) - Mission: “Revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.” ## Products & Services - **[NuLink™ D2D PHY](https://eliyan.com/about/)**: Die-to-die interconnect PHY supporting industry standards (BoW and UCIe) and proprietary simultaneous-bidirectional (SBD) technology. Delivers 4× the bandwidth and 2× the power efficiency of alternatives in advanced or standard packaging, with bump pitches from 40–130 microns. - **[NuLink™-XD](https://linkedin.com/company/eliyan-corporation)**: A new class of power-reach configurable 224G PAM4 SerDes for chip-to-chip and chip-to-module applications, targeting the lowest-power electro-optical modules for AI scale-up networks. Up to 40% lower power than competing solutions. ## Market Standing - **Valuation**: $1 billion (as of July 2026 Series C) - **Annual Revenue**: $3.5 million (2025); forecasts hundreds of millions by end of 2027 [reuters.com](https://www.cbinsights.com/company/eliyan) - **Total Funding**: $295 million (conflicting reports: other sources state $150M total); includes $145M Series C led by Seligman Ventures (July 2026), $60M Series B led by Samsung Catalyst Fund and Tiger Global (March 2024), $40M Series A led by Tracker Capital (Nov 2022). - **Notable Investors/Partners**: Seligman Ventures (board seat for Umesh Padval), Cisco Systems, Lumentum, Samsung Catalyst Fund, Tiger Global Management, Tracker Capital, VentureTech Alliance. - **Growth Signals**: Headcount of 73 employees with +6.7% monthly growth; 21 active job postings (quarterly trend +2,000%); expects to start chiplet shipments in 2026; expanding across 6 countries (US, Germany, Netherlands, Canada, India, Israel). ## Competitive Advantages - Breakthrough die-to-die interconnect architecture (invented by founder Ramin Farjadrad in 2016) that achieves 4× bandwidth and 2× power efficiency versus competing IP. - Works with standard packaging (wide range of bump pitches), reducing cost and complexity for chip designers. - Independent alternative to Broadcom/Marvell in the chiplet interconnect space, giving custom AI chip makers a neutral, high-performance option. ## Strategic Focus - Solving the growing data-movement bottleneck in AI compute (GPUs often idle 30–40% waiting for data). - Scaling NuLink and NuLink-XD platforms to support both chip-to-chip and chip-to-module applications for next-generation AI infrastructure. - Ramping chiplet production and licensing revenue, targeting hundreds of millions in sales by 2027. ## Why Work Here - On-site culture with offices in Santa Clara (HQ), Vancouver (BC), and other global locations; no remote/hybrid mentioned. - Engineering-heavy team (54% technical roles) with a fast-paced startup environment and deep expertise from companies like Marvell, Intel, AMD, and Synopsys. - Opportunity to work on cutting-edge semiconductor interconnect technology that directly impacts AI performance. - Active hiring across digital design, verification, DFT, physical design, optical engineering, and program management. ## Sources 1. [eliyan.com/about](https://eliyan.com/about/) 2. [jobs.lever.co/eliyan](https://jobs.lever.co/eliyan) 3. [linkedin.com/company/eliyan-corporation](https://linkedin.com/company/eliyan-corporation) 4. [cbinsights.com/company/eliyan](https://www.cbinsights.com/company/eliyan) 5. [reuters.com (via CNA)](https://www.cbinsights.com/company/eliyan) (Note: embedded Reuters article on CB Insights page) 6. [eliyan.com/careers](https://eliyan.com/careers/) ## Other roles at Eliyan - [Program Management - Principal / Sr. Principal Technical Program Manager – IP, ASIC & Chiplet Platforms](https://feeny.ai/job/program-management-principal-sr-principal-technical-program-manager-ip-asic-29s06vbpaq89) — Bay Area - [Program Management - Principal TPM – Packaging, SI/PI & System Integration](https://feeny.ai/job/program-management-principal-tpm-packaging-si-pi-system-integration-eliyan-bay-2dhawebwestt) — Bay Area - [Silicon Validation, Test & Characterization Engineer (title will reflect experience)](https://feeny.ai/job/silicon-validation-test-characterization-engineer-title-will-reflect-experience-9n726paagrw8) — Bay Area - [Optical - Director, OE Development (DOD)](https://feeny.ai/job/optical-director-oe-development-dod-eliyan-bay-area-hn4sqg6j0g19) — Bay Area - [DV - Staff (+) Verification Engineer -  AMS modeling](https://feeny.ai/job/dv-staff-verification-engineer-ams-modeling-eliyan-bay-area-vancouver-canada-27k4khnvjx3y) — Bay Area / Vancouver, Canada / Toronto, Canada - [PD - Sr Staff - Physical Verification Lead | Signoff & DRC](https://feeny.ai/job/pd-sr-staff-physical-verification-lead-signoff-drc-eliyan-bay-area-jmkanxqtq810) — Bay Area - [PD - Sr Staff — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |](https://feeny.ai/job/pd-sr-staff-cad-design-methodology-rtl-to-gdsii-flow-advanced-node-methodology-gtnhek1texp8) — Bay Area - [DV - Principal Digital Verification Engineer](https://feeny.ai/job/dv-principal-digital-verification-engineer-eliyan-vancouver-bc-or-bay-area-jttvf7k0jdc6) — Vancouver Bc OR Bay Area, CA - [DV - Staff Verification Engineer - Serdes](https://feeny.ai/job/dv-staff-verification-engineer-serdes-eliyan-bay-area-vancouver-canada-toronto-3sesn9ej7d97) — Bay Area / Vancouver, Canada / Toronto, Canada - [Photonics IC Validation and Characterization Engineer (title will reflect experience)](https://feeny.ai/job/photonics-ic-validation-and-characterization-engineer-title-will-reflect-kj77ht3q4rp9) — Bay Area