---
title: 'ASIC Technical Program Manager at Etched'
canonical: 'https://feeny.ai/job/asic-technical-program-manager-etched-san-jose-0hvkrvanrg90'
type: 'job'
last_seen: '2026-10-12'
---

# ASIC Technical Program Manager at Etched

- **Company:** [Etched](https://feeny.ai/companies/etched)
- **Location:** San Jose, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-05-01
- **Last confirmed live:** 2026-10-12
- **Apply:** https://jobs.ashbyhq.com/etched/bdec1a6d-300b-47fc-a551-3c937d76fee0/application

**Skills:** ASIC Tape-out, RTL-to-GDSII Flow, Physical Design, Design for Test (DFT), Design for Verification (DV), Synthesis Restarts, EDA Vendors, Program Management

> The ASIC Technical Program Manager drives technical execution for AI inference systems, coordinating across Physical Design, DFT, DV, and RTL teams. This hands-on role involves managing vendor relationships, mitigating risks, and ensuring timely tape-out and synthesis milestones in a fast-paced semiconductor environ...

## Job description

## About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary Etched is seeking a highly skilled and motivated ASIC Technical Program Manager to join our silicon team. This is a hands-on, high-accountability role for someone who has lived inside the ASIC development cycle and can drive technical execution, not just track it. You will own program coordination across Physical Design, DFT, DV, and RTL teams while managing relationships with external vendors including IP providers, implementation partners, and EDA tool vendors. The ideal candidate has real tape-out experience, understands the full RTL-to-GDSII flow, and operates with the urgency and proactivity that a first-silicon program demands.

## Key Responsibilities

- Cross-Functional Technical Coordination: Own program management across Physical Design, DFT, DV, RTL, and Post-Silicon teams. Understand inter-team dependencies - know who owns what, when handoffs need to happen, and what needs to be signed off before downstream work can begin (e.g., RTL version gates for synthesis, DFT insertion checkpoints, ECO cycles).
- Vendor Management: Engage directly with external vendors, including EDA partners and implementation partners. Hold vendors accountable to timelines and deliverables. Be prepared to push back, defend Etched’s technical requirements, and escalate when needed.
- Risk Identification and Mitigation: Proactively surface critical path risks, schedule slippage, and cross-team blockers. Develop mitigation strategies in partnership with engineering leads and escalate appropriately to technical and executive stakeholders.
- Project Planning and Execution: Manage the scheduling and execution of complex, multi-team hardware programs. Keep projects on track across tape-out milestones, synthesis respins, and signoff cycles.
- Stakeholder Communication: Provide regular, clear updates to engineering leads, VP-level stakeholders, and executive leadership on project status, risks, and decisions required. Set the tone for meetings, facilitate alignment, mediate technical disagreements, and drive to decisions.
- Process Coordination: Work with ops and engineering teams to maintain accurate tracking of program state, action owners, and open items. Support the adoption of tooling and dashboards that improve engineering visibility - though dashboard creation itself sits with the ops team.
- Technical Acumen: Bring enough ASIC domain knowledge to communicate credibly with engineers across the design stack and with external partners. You don’t need to be a designer, but you need to know the difference between a .3 and .5 RTL release, understand where DFT fits in the flow, and have a feel for what a synthesis restart actually involves.

You may be a good fit if you have (Must-have qualifications)

- At least one full ASIC tape-out under your belt. You should be able to speak fluently to what that process looks like end-to-end.
- Solid understanding of the RTL-to-GDSII flow, including where Physical Design, DFT, DV, and RTL teams intersect and hand off to each other.
- 5+ years of experience in technical program management, engineering program management, or a closely related role within the semiconductor or hardware space.
- Experience working directly with external EDA vendors or implementation partners - you’ve been in those rooms and know how to hold your ground.
- Exceptional follow-through and proactivity. You chase down dependencies; you don’t wait for them to surface.
- Strong communication and facilitation skills - you set a productive tone in meetings, keep discussions on track, and bring people to alignment.
- Comfort with fast-paced, ambiguous startup environments where priorities shift and programs evolve quickly.
- Bachelor’s degree in Engineering, Computer Science, or a related field.

## Benefits

- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2.5k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in our office
- Unlimited compute budget subject to ROI justification

## How we’re different

Etched believes in the [Bitter Lesson](http://www.incompleteideas.net/IncIdeas/BitterLesson.html). We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

## About Etched

## Company Overview
- **One-liner**: Etched designs and manufactures specialized ASICs (application-specific integrated circuits) that are hardwired to run transformer-based AI models, offering an order-of-magnitude improvement in inference cost and energy efficiency over general-purpose GPUs.
- **Entity Type**: Private (Series B / later stage; total raised $800M as of June 2026)
- **Headquarters**: San Jose, California, USA (also has offices in Cupertino, CA; Sacramento, CA; and small presence in Taiwan, Canada, UK, Bulgaria)
- **Founded**: 2022
- **Founders**: Gavin Uberti (CEO), Robert Wachen (President & COO), Chris Zhu (Co-Founder)

## Core Business
- **Primary industry**: AI hardware / semiconductor design / computer hardware manufacturing
- **Target customers**: Frontier AI labs, hyperscalers, and enterprises running large-scale transformer inference workloads (B2B, enterprise)
- **Mission / purpose**: Build hardware for superintelligence – specifically, the world’s most powerful servers for transformer inference.

## Products & Services
- **Sohu Chip (ASIC)**: A transformer-specific ASIC manufactured by TSMC. It burns the transformer architecture directly into silicon, eliminating the overhead of general-purpose GPUs for inference.
- **Frontier Inference Clusters**: Full-stack systems that bundle the Sohu chip with custom-designed racks, networking, and software. Customers place orders for complete systems, not just chips. Etched claims they deliver more tokens per dollar and per watt for dense models, sparse MoEs, diffusion models, and more.
- **Software Stack**: Includes compiler and runtime optimizations built by a team with deep experience (former Apache TVM developer, ex-Google TPU software lead).

## Market Standing
- **Valuation**: $5 billion post-money valuation (as of December 2025 / disclosed June 2026)
- **Key Metric**: $1 billion in contract orders (booked) for its systems; total funding of $800M (including an unannounced $500M round closed Dec 2025 led by Stripes)
- **Notable Investors**: Stripes (lead), VentureTech Alliance, Jane Street, Hudson River Trading, Two Sigma, Ribbit Capital. Angel investors include Andrej Karpathy, Geoffrey Hinton, Fei-Fei Li, Arthur Mensch, Scott Wu, Stanley Druckenmiller, Peter Thiel. Earlier backers: Positive Sum, Primary Venture Partners.
- **Growth Signals**:
  - Headcount: 258 employees (as of mid-2026), up 141% year-over-year
  - 100+ active job postings across engineering, operations, and business functions
  - $500M raise in late 2025; first chip manufactured by TSMC in 2025 and now being tested with customers
  - Talent sources include Google (21), Apple (17), NVIDIA (16), Tesla (11), Intel (10), AMD (5)

## Competitive Advantages
- **Transformer-specific architecture**: Unlike GPUs (which are general-purpose), Etched’s chip is hardwired only for transformer operations, enabling drastically lower cost and latency for today’s dominant AI model architecture.
- **Full-stack system play**: By selling entire inference clusters (chip + rack + software), Etched captures more value and delivers a turnkey solution competitive with NVIDIA’s DGX/HGX systems.
- **Deeply experienced leadership**:
  - CEO Gavin Uberti (Harvard math researcher, AI compiler expert, Apache TVM contributor)
  - President Robert Wachen (co-founded Prod AI incubator; Thiel Fellow)
  - VP of Platform (ex-NVIDIA 22 years, built HGX/DGX systems)
  - VP of Software (ex-Google DeepMind, lead TPU v1–v5 software)
  - Chief Architect Saptadeep Pal (former Auradine co-founder, chiplet expert)
  - VP of Hardware Engineering Ajat Hukkoo (ex-Cypress CTO, shipped >$1B revenue products)

## Strategic Focus
- **Scale manufacturing and customer deliveries**: With the first chip successfully fabricated, the company is now testing production systems and aims to fulfill $1B in pre-orders.
- **Expand engineering talent**: Aggressively hiring across silicon design, validation, infrastructure, optics, and software to support volume ramp.
- **Maintain technological lead**: Continue refining the ASIC for future transformer variants and MoE mixtures while building out a partner ecosystem.

## Why Work Here
- **Mission-driven, high-impact engineering**: “Building the hardware for superintelligence” – the company is solving one of the hardest problems in compute (inference efficiency) with a focused team.
- **Top-tier team and learning environment**: Colleagues from Google, NVIDIA, Apple, Tesla, Broadcom, and Intel; exposure to full-stack chip-to-system design.
- **In-office culture**: All roles are in-office (Cupertino and San Jose, CA). The company emphasizes on-site collaboration for hardware development. Notable perks are not heavily advertised, but compensation is competitive for the AI hardware space (equity-heavy).
- **Growth trajectory**: 141% headcount growth YoY, hundreds of open roles, and a $5B valuation signal strong backing and career acceleration potential.
- **Intellectual challenge**: Work on chip simulation, RTL design, system validation, or software infrastructure for cutting-edge AI inference.

## Sources
1. [etched.com/careers](https://www.etched.com/careers)
2. [builtin.com/company/etched](https://builtin.com/company/etched)
3. [linkedin.com/company/etched-ai](https://www.linkedin.com/company/etched-ai)
4. [cbinsights.com/company/etched](https://www.cbinsights.com/company/etched)
5. [techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/](https://techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/)

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