--- title: 'Avionics Design Engineer at Logos Space' canonical: 'https://feeny.ai/job/avionics-design-engineer-logos-space-mountain-view-ds2axf0k89e6' type: 'job' last_seen: '2026-09-09' --- # Avionics Design Engineer at Logos Space - **Company:** Logos Space - **Location:** Mountain View, CA / San Diego, CA - **Compensation:** $140k–$190k - **Employment:** full-time - **Work type:** hybrid - **Posted:** 2026-05-07 - **Last confirmed live:** 2026-09-09 - **Apply:** https://jobs.ashbyhq.com/logos-space/273c0816-cfcf-4a34-a9b3-9ade0ace1893/application **Skills:** Electrical design, Signal integrity analysis, Power integrity analysis, Ansys SIwave, HyperLynx, High-speed interfaces, Ethernet, RS422/RS485, CAN, SPI, Monte Carlo analysis, Parts stress analysis, PCB design, Altium, Oscilloscopes, Power supplies, Spectrum analyzers, PCBA manufacturing, Simetrix/Simplis, LTSpice > The Electrical Engineer leads the design, development, and validation of flight avionics hardware for LEO satellites. Responsibilities include component selection, PCB design, worst-case analysis, and product delivery from concept through on-orbit operations. ## Job description Logos Space is building the world's first Low Earth Orbit (LEO) satellite network with built-in capacity and resilience from day one. We are defining a new category—Provable Path Independence—delivering assured, high-performance broadband and cloud network connectivity to enterprise and government customers operating in the world's most demanding environments. Led by veteran aerospace and networking engineers, Logos is building hardware engineered to perform under any condition. ## The Role & Impact As a Avionics Design Engineer at Logos, you will not just draw schematics—you will architect, build, and field high-bandwidth flight processing units and avionics that power our next-generation LEO constellation. You will own flight hardware across its entire lifecycle, taking vague, complex design concepts and translating them into flight-ready hardware that survives and thrives on-orbit. ## Key Responsibilities - End-to-End Design Ownership: Architect and design flight avionics, high-speed processing boards, and payload digital systems from initial architecture through schematic capture, layout guidance, and bring-up. - Advanced Analysis: Conduct Signal Integrity (SI), Power Integrity (PI), Worst-Case Circuit Analysis (WCCA/Monte Carlo), and Parts Stress/Derating analysis to guarantee high-reliability performance in space. - Cross-Functional Collaboration: Partner directly with Flight Software, RF, Mechanical, and Thermal engineering teams to optimize system-level tradeoffs, board pinouts, and physical packaging. - Manufacturing & Bring-Up: Collaborate with Contract Manufacturers (CMs) for DFM/DFA reviews, PCBA assembly oversight, rapid prototyping, and hands-on lab troubleshooting. - Validation & Flight Qualification: Generate comprehensive technical drawings, specifications, test procedures, and reports; lead board-level and system-level environmental testing (thermal vacuum, vibration, EMI/EMC). ## Basic Qualifications - Education: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related STEM field. - Experience: 5+ years of hands-on experience in digital electrical design and hardware analysis. - High-Speed Interfaces: Proven experience designing with high-speed digital interfaces (e.g., DDR4/DDR5, 1G/10G Ethernet, PCIe) and standard communication buses (CAN, RS-422/RS-485, SPI, I2C). - SI/PI Analysis: 3+ years of hands-on experience using Signal and Power Integrity modeling tools (e.g., Ansys SIwave, HyperLynx). - ECAD Proficiency: Advanced design experience with professional schematic capture and PCB layout tools (preferably Altium Designer). - Space / High-Reliability Rigor: Demonstrated track record with Worst-Case Analysis (WCCA), parts stress evaluation, and derating. - Lab Equipment Mastery: Deep proficiency with lab diagnostic tools (oscilloscopes, logic analyzers, spectrum analyzers, power supplies). - U.S. Person Status: Must be a U.S. Citizen or Permanent Resident due to export control regulations (ITAR/EAR). ## Preferred Qualifications - Master's degree in Electrical Engineering or STEM field. - Experience designing high-density FPGA or SoC processing systems for space or aerospace applications. - Familiarity with industry space derating and design standards (e.g., EEE-INST-002, ECSS-Q-ST-30-11C, IPC-2221). - Hands-on experience with circuit simulation software (LTSpice, SIMetrix/SIMPLIS). - Knowledge of EMI/EMC/ESD design mitigations and testing protocols for space flight hardware. - Scripting and test automation skills using Python or MATLAB. - Ability and willingness to obtain and maintain a U.S. Government Top Secret Security Clearance. Engineering Culture & Benefits - Fast Iteration Cycles: In-house rapid prototyping and dedicated test lab access to validate designs quickly. - Ownership & Autonomy: No silos, no politics—we encourage debate, make data-driven decisions fast, and commit together. - Location Flexibility: On-site opportunity in either Mountain View, CA or San Diego, CA with relocation support available. Logos Space Services is an equal opportunity employer committed to fostering creativity, curiosity and diverse perspectives among employees. We seek to create an environment where everyone can reach their full potential and drive outstanding results. All qualified applicants will receive consideration for employment without regard to race, national origin, age, sex, religion, disability, sexual orientation, marital status, veteran status, gender identity or expression, or any other basis protected by local, state, or federal law. This policy applies with regard to all aspects of one's employment, including hiring, transfer, promotion, compensation, eligibility for benefits, and termination. Offers will be contingent on the candidate's ability to access export-controlled information under U.S. law. ## About Logos Space ## Company Overview - **One-liner**: Logos Space is building a low Earth orbit (LEO) satellite constellation to deliver a secure, resilient, high-performance private network for government and enterprise customers. - **Entity Type**: Private (Series A) - **Headquarters**: Mountain View, California, USA (with additional office in Redwood City, CA) - **Founded**: 2024 - **Founders**: Milo Medin (former Google VP of access services and NASA project manager) ## Core Business - **Primary industries**: Satellite communications, aerospace & defense, telecommunications - **Target customers**: Government agencies (defense, intelligence, civil) and large enterprises requiring secure, guaranteed connectivity – distinct from consumer-focused satellite broadband. - **Mission / purpose**: Deliver a next-generation private network that is purpose-built for contested communications environments, offering security, resilience, and fiber-like performance where fiber doesn’t go. ## Products & Services - **Logos LEO Constellation**: A planned network of up to 4,178 satellites operating in Q, V, Ka and E frequency bands (FCC licensed). Capabilities include symmetric multi-gigabit throughput, Layer 2 MPLS networking, end-to-end encryption, and electronic warfare (EW) resilience. Designed as a dual-use system (civilian and military) with hardened satellites and a mesh architecture to maintain service during disruption. ## Market Standing - **Valuation/Total Funding**: USD $50 million (Series A led by US Innovative Technology Fund, announced June 2025). Total funding to date is $50M, with USIT as the sole investor. - **Key Metric**: 22–38 employees (rapidly growing; headcount up 416% year-over-year); 59 active job postings as of mid-2026. - **Notable Investors / Partners**: US Innovative Technology Fund (chaired by serial entrepreneur Thomas Tull). Key hires from SpaceX, NASA, Airbus, OneWeb, and Apollo Fusion. - **Growth Signals**: FCC grant for satellite spectrum license (Feb 2026) authorizing up to 4,178 satellites; emerged from stealth in Oct 2024; aiming for first operational satellite in late 2027; aggressive hiring across engineering, RF, software, and business development. ## Competitive Advantages - **Dual-use focus**: Purpose-built for government and enterprise, not consumer – enabling higher security, guaranteed service, and resilience requirements. - **EW-resilient design**: Architecture minimizes signal disruption and resists jamming through high-elevation angles, tightly focused beams, and hardened satellites. - **Unique spectrum portfolio**: FCC-approved use of Q, V, Ka and E bands – high-frequency bands that are less congested and offer higher bandwidth. - **Fiber-like performance at scale**: Symmetric multi-Gbps throughput with Layer 2 MPLS and end-to-end encryption, filling a gap underserved by existing LEO providers. - **Experienced leadership**: Founder Milo Medin (Google access services, NASA) and a deeply experienced technical team from top aerospace and satellite organizations. ## Strategic Focus - Complete critical design decisions, select partners, and build prototypes. - Scale engineering team from ~30 to 70+ employees through 2026. - Deploy first operational satellite by late 2027 and begin constellation build-out. - Continue engaging with U.S. regulators and potential government/enterprise customers. ## Why Work Here - **Mission-driven**: Work on a “next-generation” communications infrastructure that addresses real national security and enterprise resilience needs. - **Culture & values**: No silos, no politics; treat people with respect; debate, decide, commit; continuous learning; customer focus. Operating principles explicitly discourage unprofessional behavior. - **Growth opportunity**: Start-up stage with significant funding, clear milestone, and aggressive hiring – opportunity to shape technology and team. - **Work policy**: In-office (typically 5 days a week) at Mountain View or Redwood City, CA locations. - **Teams**: Engineering, product, operations, and business development roles heavily represented; emphasis on space, RF, embedded software, and network engineering. ## Sources 1. [logosspace.com](https://logosspace.com/) 2. [logosspace.com/careers](https://logosspace.com/careers/) 3. [builtin.com](https://builtin.com/company/logos-space) 4. [linkedin.com/company/logosspace](https://www.linkedin.com/company/logosspace) 5. [spacenews.com](https://spacenews.com/logos-nets-50-million-to-advance-plans-for-more-than-4000-broadband-satellites/) ## Other roles at Logos Space - [Senior Control Plane Software Engineer](https://feeny.ai/job/senior-control-plane-software-engineer-logos-space-mountain-view-qnzb1c8araxm) — Mountain View, CA - [Lead, Satellite Optical Payload Engineering](https://feeny.ai/job/lead-satellite-optical-payload-engineering-logos-space-mountain-view-svm1ntn0nkp6) — Mountain View, CA / San Diego, CA - [Security Assurance Lead](https://feeny.ai/job/security-assurance-lead-logos-space-mountain-view-akhxk4y5y6nr) — Mountain View, CA / San Diego, CA - [Lead Security Architect – Cloud Platform & Network Security](https://feeny.ai/job/lead-security-architect-cloud-platform-network-security-logos-space-mountain-qag8r7dy3q5z) — Mountain View, CA / San Diego, CA - [Lead Security Engineering - Terminals](https://feeny.ai/job/lead-security-engineering-terminals-logos-space-mountain-view-1fyd97p8s99j) — Mountain View, CA / San Diego, CA - [Lead Product Security Engineer – Supply Chain & Hardware](https://feeny.ai/job/lead-product-security-engineer-supply-chain-hardware-logos-space-mountain-view-xn7x7a8vf8qc) — Mountain View, CA / San Diego, CA - [Senior FPGA/ASIC Modem Engineer](https://feeny.ai/job/senior-fpga-asic-modem-engineer-logos-space-mountain-view-31eexrcq4b2a) — Mountain View, CA - [Lead, Financial Planning & Analysis](https://feeny.ai/job/lead-financial-planning-analysis-logos-space-mountain-view-1ecf7pcs0n7r) — Mountain View, CA - [Legal Counsel](https://feeny.ai/job/legal-counsel-logos-space-mountain-view-f01zmwega5e7) — Mountain View, CA / San Diego, CA - [Lead Phased Array Antenna Engineer](https://feeny.ai/job/lead-phased-array-antenna-engineer-logos-space-mountain-view-y0tqkn8es94v) — Mountain View, CA / San Diego, CA