--- title: 'CAD Back-end Lead at Velaura' canonical: 'https://feeny.ai/job/cad-back-end-lead-velaura-bengaluru-f130hrc0va9c' type: 'job' last_seen: '2026-10-16' --- # CAD Back-end Lead at Velaura - **Company:** Velaura - **Location:** Bengaluru, India - **Employment:** full-time - **Work type:** onsite - **Posted:** 2026-09-16 - **Last confirmed live:** 2026-10-16 - **Apply:** https://jobs.lever.co/velaura/0095a809-c88f-4ee2-a0a4-231fc40f569a ## Job description ## Role Overview We are looking for a CAD Back-end Lead to build, integrate, and support the design flows used by Velaura’s Custom Design and Physical Design teams. This role will own the CAD framework supporting custom design, parasitic extraction, circuit simulation, characterization, physical implementation, timing and power analysis, physical verification, and tapeout. You will work closely with Custom Circuit Design, Custom Layout, Characterization, Physical Design, STA, Power Integrity, Physical Verification, and CAD Infrastructure teams to translate domain-specific methodologies into qualified, scalable, and reproducible production flows. The functional teams will own design methodology, execution, QoR targets, and signoff criteria. This role will own flow architecture, EDA tool integration, automation, version control, release qualification, regression infrastructure, documentation, and production support. The ideal candidate combines a strong understanding of custom-design and back-end workflows with hands-on expertise in EDA integration, software development, scripting, regression automation, agentic AI development, and advanced-node enablement. Success in this role will be measured by flow reliability, ease of use, turnaround time, reproducibility, and engineering productivity. ## Responsibilities - Develop, integrate, qualify, release, and support CAD flows spanning Custom Design, physical implementation, and Physical Verification across multiple projects and advanced process technologies. - Own and develop reusable CAD frameworks for custom design and custom layout, as well as block-level, hierarchical, subsystem-level, and full-chip physical implementation. - Integrate EDA tools from Cadence, Synopsys, Siemens EDA, Ansys, and other vendors into consistent, version-controlled, and reproducible design environments. - Partner with domain experts to translate Custom Design, Characterization, Physical Design, STA, Power Integrity, and Physical Verification methodologies into automated production flows. - Integrate and qualify foundry PDKs, technology files, standard-cell libraries, memories, IP collateral, RC corners, extraction decks, signoff rule decks, and EDA tool configuration files. - Own back-end flow releases, including configuration management, regression testing, qualification, documentation, deployment, versioning, and rollback. - Establish source-control and release-management practices using Git, GitLab, Perforce, or equivalent platforms, including branching, tagging, code reviews, release baselines, and change tracking. - Build regression infrastructure to validate flow functionality, EDA tool upgrades, PDK updates, methodology changes, and design collateral before production deployment. - Develop automated quality checks and dashboards covering flow status, runtime, resource usage, failures, design quality, and key QoR metrics. - Work with central CAD and Infrastructure teams on compute requirements, job scheduling, storage, EDA tool deployment, license usage, and capacity planning for Custom Design and back-end workloads. - Partner with foundries, IP providers, and EDA vendors to resolve issues involving EDA tools, PDKs, technology files, rule decks, and design methodologies. - Evaluate new EDA technologies based on measurable improvements in quality of results, turnaround time, scalability, reliability, engineering productivity, and cost. - Actively use AI-assisted coding and engineering tools for software development, test generation, code review, documentation, log analysis, debugging, and flow optimization. - Architect and develop agentic AI workflows for EDA flow orchestration, regression monitoring, failure classification, root-cause analysis, QoR comparison, knowledge retrieval, and production support. - Integrate AI agents with EDA tools, job schedulers, version-control systems, regression databases, dashboards, and internal engineering knowledge repositories. - Establish appropriate security, access-control, IP-protection, validation, and human-approval mechanisms for applying AI to proprietary design data and production EDA environments. - Define measurable success criteria for AI-assisted workflows and transition successful prototypes into qualified production use. - Establish coding standards, code-review practices, validation requirements, documentation standards, and release processes for back-end CAD development. - Mentor CAD engineers and promote strong practices in software development, automation, version control, regression testing, agentic AI development, and production flow support. Required Qualifications - Deep understanding of the ASIC development lifecycle, with strong knowledge of custom design, physical implementation, signoff, Physical Verification, and tapeout flows. - Experience developing and supporting CAD flows across multiple successful ASIC or SoC programs. - Experience integrating EDA tools from Cadence, Synopsys, Siemens EDA, Ansys, and/or other major EDA vendors. - Familiarity with tools such as Cadence Virtuoso, Innovus, Voltus, and Quantus; Synopsys Fusion Compiler, PrimeTime, StarRC, HSPICE, and PrimeSim; Siemens Calibre; and Ansys RedHawk-SC. - Experience integrating foundry PDKs, technology files, timing libraries, physical libraries, extraction decks, verification rule decks, and third-party IP collateral. - Strong software-development and scripting skills using Python, Tcl, Bash, Perl, or similar languages. - Hands-on experience with version-control and collaboration platforms such as Git, GitLab, Perforce, or equivalent tools. - Experience with branching, tagging, merge requests, code reviews, release baselines, configuration management, and rollback strategies. - Experience with automated regression testing, continuous integration, release management, and reproducible engineering practices. - Hands-on experience using modern AI coding assistants and engineering tools as part of software or CAD flow development. - Experience developing AI- or LLM-based applications or agentic workflows that integrate tools, APIs, engineering data, and knowledge sources. - Ability to validate AI-generated code, analysis, and recommendations before deployment in production semiconductor design flows. - Practical understanding of data security, access control, confidentiality, and IP protection when applying AI to proprietary engineering environments. - Strong understanding of Linux environments, distributed compute, batch scheduling, storage systems, and license-dependent EDA workloads. - Strong debugging and root-cause-analysis skills across EDA tools, scripts, design databases, PDK collateral, and compute environments. - Experience supporting production design teams and resolving time-critical flow issues during major project milestones and tapeout. - Excellent communication skills and the ability to collaborate with global Custom Design, Physical Design, STA, Power Integrity, Physical Verification, CAD, foundry, and EDA-vendor teams. ## Preferred Qualifications - Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, VLSI, Computer Science, or a related discipline. - Experience enabling leading-edge FinFET or Gate-All-Around process technologies. - Experience building QoR dashboards, regression analytics, flow-monitoring systems, or automated failure-triage solutions. - Experience deploying production-quality agentic AI workflows for semiconductor design, EDA automation, regression triage, design-data analysis, or engineering knowledge management. - Experience developing and scaling CAD capabilities in a fast-paced or early-stage semiconductor company. Why Velaura? Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world. This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you. ## Equal Employment Opportunity and Accommodations Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans. Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: careers@velaura.ai. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis. ## About Velaura ## Company Overview - **One-liner**: Velaura (formerly Auradine) is a semiconductor and systems company building ultra-low-power compute infrastructure for AI workloads across cloud, edge, and physical AI applications. - **Entity Type**: Private (Series C, $314M total funding) - **Headquarters**: Santa Clara, California, USA - **Founded**: 2023 (as Auradine; rebranded to Velaura AI in 2026) - **Founders**: Co-founded by Rajiv Khemani (CEO), YJ Kim (President, Products), Sanjay Gupta (President, Strategy & GTM), and Manu Gulati (Chief Development Officer) ## Core Business - **Primary Industry**: Semiconductor design, AI compute infrastructure, ultra-low-power ASICs - **Target Customers**: Hyperscale data centers, AI/ML platform providers, edge computing companies, and physical AI (robotics, automotive) OEMs — primarily **B2B Enterprise** - **Mission**: To deliver proven, breakthrough, ultra-low-power compute for cloud, edge, and physical AI applications, solving the power bottleneck that constrains AI scaling. ## Products & Services - **Proprietary Ultra-Low-Power Digital Design Technology**: Patented IP and toolflow that reduces power consumption of arithmetic operations by 2–4x on leading process nodes, translating to ~$650–$1,300/chip in power savings over 3 years. Output is optimized GDS or chiplets. - **Custom AI Accelerators (ASICs)**: Full-custom silicon solutions for AI inference and training workloads, co-designed with customers (RTL input → optimized GDS). - **Engagement Model**: Customer provides RTL design and priorities; Velaura applies its proprietary methodology, low-voltage libraries, and custom circuit expertise to deliver power-optimized chip designs with proven yield and reliability. ## Market Standing - **Valuation/Market Cap**: Not publicly disclosed (private company) - **Key Metric**: **$314M total funding** across 4 rounds - Series A (2023): $71M from 6 investors - Debt Financing (2023): $10M - Series B (2024): $80M from 7 investors - Series C (2025): $153M from 8 investors - **Notable Investors/Partners**: Backed by top-tier VCs (specific names not publicly listed; investors include firms with deep semiconductor expertise) — talent sources include Qualcomm, Arm, Apple, Google, NVIDIA, Intel, Palo Alto Networks, Stripe - **Growth Signals**: - Rebranded from Auradine to Velaura AI in August 2026, signaling strategic expansion into AI compute - Added Manu Gulati (ex-NUVIA co-founder, Apple/Google silicon architect) as Co-founder & Chief Development Officer - Added Aditya Grover (Co-founder & CTO of Inception, Stanford PhD, part of the team that invented Diffusion models) as Founding Advisor - Workforce of 42 employees growing at +4.3% monthly; headcount split ~47% US / 39% India - Offices in Santa Clara, CA (HQ) and additional US location, with hiring across hardware and software engineering in Bangalore, Austin, and Boston ## Competitive Advantages - **Patented ultra-low-power digital design technology** field-proven over multiple years across tens of millions of ASICs deployed with world-class yield and reliability - **Founding team with exceptional pedigree**: seasoned entrepreneurs and technologists from Qualcomm, Marvell, NVIDIA, Intel, Palo Alto Networks, Apple, Google, and NUVIA (acquired by Qualcomm for ~$1.5B) - **Systems-level thinking**: combines deep silicon expertise with AI/ML domain knowledge to tackle power as the primary bottleneck for AI at scale - **Engagement model** that allows customers to leverage Velaura’s IP without fully outsourcing chip design — outputs optimized GDS or chiplets on latest process nodes ## Strategic Focus - **Scale ultra-low-power compute across three domains**: cloud data centers, edge/enterprise, and physical AI (robotics, autonomous systems) - **Hire aggressively** for engineering leadership: compiler development, platform software, CAD/methodology, RTL, design verification, advanced packaging, AI architecture, and hardware/software co-design - **Productize its proprietary IP** into standard offerings for hyperscalers and AI chip companies - **Continue raising capital** (largest round was $153M Series C in April 2025) to fund expansion ## Why Work Here - **Culture**: Deep engineering DNA and systems-level thinking — the team is solving one of AI’s hardest physical constraints (power) with proven silicon technology - **Growth trajectory**: Rapidly scaling startup (42 employees, +4.3% monthly headcount growth, $314M raised) with a clear path to becoming a key infrastructure provider for the AI era - **Leadership**: Led by industry veterans (NUVIA, Apple, Google, Qualcomm) who have built billion-dollar silicon companies and products powering billions of devices - **Work environment**: On-site roles in Santa Clara, CA; Austin, Texas; and Bangalore, India. Remote/hybrid policy not specified but multiple office locations suggest flexible collaboration. - **Impact**: Opportunity to work on cutting-edge AI hardware design, from architecture through tape-out and deployment, with direct impact on the power efficiency of the world’s largest AI clusters - **Notable perks**: Not publicly detailed, but the company’s focus on high-end engineering talent suggests competitive compensation, equity, and exposure to top-tier semiconductor and AI technology ## Sources 1. [velaura.ai](https://velaura.ai/introducing-velaura-ai/) 2. [velaura.ai](https://velaura.ai/team/) 3. [velaura.ai](https://velaura.ai/low-power-ai-compute/) 4. [jobs.lever.co/velaura](https://jobs.lever.co/velaura/) 5. [linkedin.com](https://linkedin.com/company/velaura-ai-inc) 6. [wellfound.com](https://wellfound.com/company/velaura-ai) (Apollo data extracted on financials and headcount) SUGGESTED_INDUSTRY: semiconductor-manufacturing-robotics-ai-infrastructure _(Note: The above slug is not in the provided list. Closest match from the list is `artificial-intelligence`. However, given the company's core business is semiconductor design and power-efficient AI compute infrastructure, `manufacturing-robotics` or `infrastructure` also fit. For strict adherence to the provided list: `artificial-intelligence` is the best single choice.)_ ## Other roles at Velaura - [Edge AI SDK Lead](https://feeny.ai/job/edge-ai-sdk-lead-velaura-santa-clara-fg28np6v11fb) — Santa Clara, CA - [RTL Engineer Memory Subsystem](https://feeny.ai/job/rtl-engineer-memory-subsystem-velaura-santa-clara-jtrax095faxj) — Santa Clara, CA - [SoC Design Verification Lead](https://feeny.ai/job/soc-design-verification-lead-velaura-santa-clara-5ffrthtymcq8) — Santa Clara, CA - [SoC Design Verification Engineer](https://feeny.ai/job/soc-design-verification-engineer-velaura-santa-clara-4re9r1jbzc50) — Santa Clara, CA - [Office Admin / Receptionist](https://feeny.ai/job/office-admin-receptionist-velaura-santa-clara-asc5tq6ff9ze) — Santa Clara, CA - [Sr Engineer CAD Pre-Silicon Front End](https://feeny.ai/job/sr-engineer-cad-pre-silicon-front-end-velaura-santa-clara-91g66vhzqqt3) — Santa Clara, CA - [Director of IT Infrastructure & Operations](https://feeny.ai/job/director-of-it-infrastructure-operations-velaura-santa-clara-46t1yb690v9g) — Santa Clara, CA - [RTL Power Engineer](https://feeny.ai/job/rtl-power-engineer-velaura-santa-clara-jyj4n03rckrf) — Santa Clara, CA - [Design Verification Engineer- AI Accelerator](https://feeny.ai/job/design-verification-engineer-ai-accelerator-velaura-santa-clara-15tk23smaz5x) — Santa Clara, CA - [Design Verification Engineer- CPU](https://feeny.ai/job/design-verification-engineer-cpu-velaura-santa-clara-d1bkx2h2dj9g) — Santa Clara, CA