---
title: 'Compiler Frontend Engineer at Normal Computing Corporation'
canonical: 'https://feeny.ai/job/compiler-frontend-engineer-normal-computing-corporation-mountain-view-xd4ytzz9zmbz'
type: 'job'
last_seen: '2026-10-29'
---

# Compiler Frontend Engineer at Normal Computing Corporation

- **Company:** Normal Computing Corporation
- **Location:** Mountain View, CA
- **Employment:** full-time
- **Work type:** hybrid
- **Posted:** 2026-10-22
- **Last confirmed live:** 2026-10-29
- **Apply:** https://jobs.ashbyhq.com/normalcomputing/ca0beabb-b825-4285-a292-3b8d0db44338

## Job description

Normal Computing | Build with Us Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London.

## The Role

Normal's hardware runs the most memory-bound parts of large-model inference inside memory itself, rather than shuttling weights to a processor. The software that makes this programmable doesn't exist yet in any standard form. Our compiler is how models reach that hardware, and new LLM architectures show up faster than most compilers can track. A new attention variant, MoE routing scheme, or quantization approach has to be represented faithfully in our compiler before it can run, let alone run fast. As a Compiler Engineer focused on frontend and model bring-up, you will extend our IR, ops, and lowering passes so new LLM architectures are supported before a customer asks for them. This is a research-adjacent seat: you are expected to follow the literature closely, and publish on behalf of Normal. Our chip is pre-silicon, so you will validate bring-up against our simulators and FPGA prototypes first, so that models are ready to run when silicon arrives.

## What You Will Own

- Model Bring-up: Bring up frontend and mid-level support for new LLM architectures in our compiler, from attention variants to MoE routing schemes. Success means new architectures run correctly on our stack soon after release, ahead of customer demand.
- IR and Lowering: Extend our IR, ops, and lowering passes to represent new architectural primitives faithfully rather than approximately, with test coverage that keeps them correct as the compiler evolves.
- Quantization and Numerics: Represent the quantization schemes and numeric formats new models use, so lowering preserves model accuracy.
- Architecture Tracking: Track the LLM architecture landscape closely enough to recommend what the team brings up next.
- Cross-Team Handoffs: Hand lowered programs to the backend compiler engineers who map them onto our hardware, and work with our LLM serving engineer to take new models from compiler support to serving.

What Makes You a Great Fit

- Hands-on ML compiler experience: you have written and shipped compiler passes
- Deep familiarity with PyTorch internals, ideally including its compilation stack (TorchDynamo, FX, torch.export)
- Working knowledge of modern LLM architectures at the level of attention mechanisms, MoE routing, and quantization schemes
- Patience for the unglamorous part of the job: getting a new architecture from “runs” to “runs correctly” to “runs correctly and fast”
- Comfort designing compiler infrastructure in a young codebase as well as extending an established one
- Comfort building software for hardware that is still evolving, from simulation through bring-up
- Fluency in Python, and familiarity with C++ or Rust

Bonus Points

- Experience with other ML compilers, such as IREE, XLA, or TVM
- Familiarity with other ML frameworks and graph formats, such as JAX or ONNX
- Experience partitioning models across devices with tensor, pipeline, or expert parallelism
- Experience with hardware-software co-design
- Experience with non-standard or in-memory hardware targets
- Contributions to open-source compiler or ML infrastructure projects

## Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our [Applicant Privacy Notice](https://normalcomputing.com/applicant-privacy-notice).

## About Normal Computing Corporation

## Company Overview
- **One-liner**: Normal Computing builds AI-accelerated EDA software and physics-based ASICs to enable ultra-efficient hardware for the AI era.
- **Entity Type**: Private (Series B; total funding $92.5M)
- **Headquarters**: New York, New York, USA
- **Founded**: 2022
- **Founders**: Faris Sbahi (CEO), Matthias Tan (Co-Founder), and team of former Google Brain/Google X engineers and scientists

## Core Business
- Primary industry: Semiconductor design (EDA) and custom silicon (ASICs), powered by AI and probabilistic computing.
- Target customers: Large semiconductor design and manufacturing institutions (B2B, enterprise).
- Mission: "Rewriting AI foundations to advance the frontier of reasoning and reliability in the physical world" and enabling a virtuous cycle of self-improving AI hardware.

## Products & Services
- **[Normal EDA](https://normalcomputing.com/)**: An AI-driven electronic design automation platform that understands design intent from specification documents, generates hierarchical test plans with traceability, creates SystemVerilog stimulus, runs simulations, and tracks coverage. It continuously learns from team feedback to accelerate verification for complex chip designs.
- **[Normal ASICs](https://normalcomputing.com/)**: Physics-based custom ASICs that relax traditional computing assumptions (stochastic, stateful, asynchronous) to unlock orders-of-magnitude more efficient compute. Designed to converge hardware with the physical dynamics of AI models.

## Market Standing
- **Valuation/Market Cap**: Not publicly disclosed.
- **Key Metric**: **Total Funding** – $92.5M across multiple rounds (Seed, Venture, Grant, Series B). Notable recent round: $50M led by **Samsung Catalyst** in March 2026 [normalcomputing.com](https://normalcomputing.com/).
- **Notable Investors**: Samsung Catalyst Fund, Intel Ignite, First Spark Ventures, Celesta Capital, ARIA. Also partners with Fraunhofer IESE (DRAMBench benchmark).
- **Growth Signals**: Headcount grew **196.3% YoY** to 54 employees; operates across 6 countries (US, UK, Denmark, Switzerland, India, Canada); actively building open-source tools (e.g., a Verilog simulator built with AI: 580K lines in 43 days).

## Competitive Advantages
- **Physics-First Approach**: Unlike traditional digital logic, Normal’s ASICs embrace stochastic, stateful, and asynchronous computing – aligning hardware with the physics of AI models for dramatic efficiency gains.
- **Full-Stack Co-Design**: The combination of AI-native EDA tools and custom silicon creates a closed loop where software and hardware are co-optimized, shortening time-to-market and enabling workload-specific ASICs.
- **Deep AI Heritage**: Founders and team hail from Google Brain and Google X, bringing deep expertise in probabilistic ML, quantum AI, and physical-world reasoning.

## Strategic Focus
- **Scaling EDA Adoption**: Expanding Normal EDA’s use among top semiconductor companies to "make chip design look more like software".
- **AI Hardware Energy Crisis**: Tackling soaring power demands of AI by delivering ultra-efficient ASICs that can be produced for every workload.
- **Open-Source & Research**: Building community trust through open benchmarks (DRAMBench) and tools (CIRCT-based verification), while advancing formal methods and AI-driven simulation.

## Why Work Here
- **Hybrid Workspace**: Flexible in-office collaboration at offices in **New York (Flatiron HQ)**, **San Francisco**, **London**, and **Copenhagen**. In-person collaboration is valued but with flexibility; free lunch, snacks, and beverages in office.
- **Lean, High-Impact Team**: Small team (54 employees) where every member drives significant impact, works directly with customers, and owns meaningful parts of the product.
- **Interdisciplinary Challenges**: Work spans AI, probabilistic software, hardware, physics, and full-stack engineering – ideal for curious, passionate problem-solvers.
- **Strong Growth Trajectory**: Rapid headcount growth (+196% YoY), recent $50M Series B, and partnerships with industry giants signal a well-funded, high-potential startup.

## Sources
1. [normalcomputing.com](https://normalcomputing.com/)
2. [normalcomputing.com/about](https://normalcomputing.com/about)
3. [linkedin.com/company/normal-computing-corporation](https://www.linkedin.com/company/normal-computing-corporation)
4. [builtin.com/company/normal-computing](https://builtin.com/company/normal-computing)
5. [jobs.ashbyhq.com/normalcomputing](https://jobs.ashbyhq.com/normalcomputing)

## Other roles at Normal Computing Corporation

- [AI Research Resident (Algorithms Codesign)](https://feeny.ai/job/ai-research-resident-algorithms-codesign-normal-computing-corporation-new-york-60jxmxr64wk5) — New York, NY
- [Engineering Manager, Compiler & Runtime](https://feeny.ai/job/engineering-manager-compiler-runtime-normal-computing-corporation-mountain-view-tt9vtnwjygvt) — Mountain View, CA
- [Events & Conferences Specialist](https://feeny.ai/job/events-conferences-specialist-normal-computing-corporation-new-york-3rgsr2f7hkhj) — New York, NY
- [Mechanical Engineer, Hardware Systems](https://feeny.ai/job/mechanical-engineer-hardware-systems-normal-computing-corporation-mountain-view-n9eqr3h1hgbh) — Mountain View, CA
- [Simulator & Debug Tools Lead](https://feeny.ai/job/simulator-debug-tools-lead-normal-computing-corporation-mountain-view-tg38bb3b0dx4) — Mountain View, CA
- [Firmware Engineer](https://feeny.ai/job/firmware-engineer-normal-computing-corporation-mountain-view-92p63r8rsgdk) — Mountain View, CA
- [TPM Lead](https://feeny.ai/job/tpm-lead-normal-computing-corporation-mountain-view-d92ny63s7jex) — Mountain View, CA
- [Hardware Engineer, DFT](https://feeny.ai/job/hardware-engineer-dft-normal-computing-corporation-mountain-view-xv7mzqfbedsx) — Mountain View, CA
- [Head of Silicon Product Engineering](https://feeny.ai/job/head-of-silicon-product-engineering-normal-computing-corporation-mountain-view-c514zrdswrxf) — Mountain View, CA
- [Hardware Engineer, Performance Modeling](https://feeny.ai/job/hardware-engineer-performance-modeling-normal-computing-corporation-mountain-e9pgdhrbq1cy) — Mountain View, CA