--- title: 'DFT (Design For Test) Engineer at Etched' canonical: 'https://feeny.ai/job/dft-design-for-test-engineer-etched-san-jose-6qgj6z8wjbzs' type: 'job' last_seen: '2026-10-19' --- # DFT (Design For Test) Engineer at Etched - **Company:** [Etched](https://feeny.ai/companies/etched) - **Location:** San Jose, CA - **Employment:** full-time - **Work type:** onsite - **Posted:** 2026-02-28 - **Last confirmed live:** 2026-10-19 - **Apply:** https://jobs.ashbyhq.com/etched/ca25e600-e2e8-4111-b672-ee3a830a8ecf/application > Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep... ## Job description ## About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are seeking a highly skilled and motivated Design For Testability (DFT) Engineer to join our dynamic team. The ideal candidate will be responsible for ensuring the robust testability of integrated circuits (ICs) from the design phase through to production. This role is crucial in improving the efficiency and effectiveness of our testing processes, thereby enhancing overall product quality. ## Key responsibilities - Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation. - Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST (MBIST). - Collaborate cross-functionally with design and verification teams to ensure DFT requirements are addressed early and consistently throughout the design cycle. - Analyze test results and silicon debug data to provide design feedback and drive improvements in coverage, yield, and reliability. - Create and execute comprehensive DFT verification plans to validate the correct implementation and functionality of all DFT features. - Apply simulation-based and formal verification techniques to ensure high confidence in DFT logic correctness. - Conduct internal DFT audits and design reviews to proactively identify and resolve gaps in testability or coverage. - Support silicon bring-up, debug, and failure analysis during post-silicon validation to ensure successful product launch. - Partner with test engineering teams to develop and optimize Automated Test Equipment (ATE) programs for volume production. - Generate production-quality test patterns and ensure robust failure analysis capability in high-volume environments. - Collaborate with manufacturing and quality teams to implement data-driven test process improvements and monitor long-term product health. - Ensure test strategies are aligned with product milestones, manufacturing timelines, and quality/reliability targets. - Author and maintain detailed documentation for DFT architecture, test plans, procedures, and debug guides. - Share best practices through training sessions, onboarding, and mentorship to enhance DFT awareness across design and test teams. - Stay current with emerging DFT technologies, industry trends, and evolving standards to continually improve internal methodologies. You may be a good fit if you have - 10+ years of experience in DFT engineering with a track record of successful test implementations for ASIC or SoC products. - A deep understanding of digital design, verification methodologies, and DFT implementation practices. - Proficiency in System Verilog and fluency with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent). - Scripting and automation experience using Python, Perl, or TCL to streamline DFT implementation and test processes. - Track record of leading DFT initiatives across multiple product generations in high-performance or high-volume silicon environments. - Strong analytical and debugging skills, with the ability to work across teams to resolve complex testability issues. - Excellent communication and collaboration abilities, with a focus on clarity and cross-functional alignment. - A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred). Strong candidates may also have experience with - Mixed-signal DFT methodologies and integration of analog testability into SoC workflows. - Industry standards such as IEEE 1149.1 (JTAG), IEEE 1500, and experience applying them in complex designs. - Yield analysis, product engineering, and contributions to test cost reduction and quality improvement programs. ## Benefits - Medical, dental, and vision packages with generous premium coverage - $500 per month credit for waiving medical benefits - Housing subsidy of $2.5k per month for those living within walking distance of the office - Relocation support for those moving to San Jose (Santana Row) - Various wellness benefits covering fitness, mental health, and more - Daily lunch + dinner in our office - Unlimited compute budget subject to ROI justification ## How we’re different Etched believes in the [Bitter Lesson](http://www.incompleteideas.net/IncIdeas/BitterLesson.html). We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed. ## About Etched ## Company Overview - **One-liner**: Etched designs and manufactures specialized ASICs (application-specific integrated circuits) that are hardwired to run transformer-based AI models, offering an order-of-magnitude improvement in inference cost and energy efficiency over general-purpose GPUs. - **Entity Type**: Private (Series B / later stage; total raised $800M as of June 2026) - **Headquarters**: San Jose, California, USA (also has offices in Cupertino, CA; Sacramento, CA; and small presence in Taiwan, Canada, UK, Bulgaria) - **Founded**: 2022 - **Founders**: Gavin Uberti (CEO), Robert Wachen (President & COO), Chris Zhu (Co-Founder) ## Core Business - **Primary industry**: AI hardware / semiconductor design / computer hardware manufacturing - **Target customers**: Frontier AI labs, hyperscalers, and enterprises running large-scale transformer inference workloads (B2B, enterprise) - **Mission / purpose**: Build hardware for superintelligence – specifically, the world’s most powerful servers for transformer inference. ## Products & Services - **Sohu Chip (ASIC)**: A transformer-specific ASIC manufactured by TSMC. It burns the transformer architecture directly into silicon, eliminating the overhead of general-purpose GPUs for inference. - **Frontier Inference Clusters**: Full-stack systems that bundle the Sohu chip with custom-designed racks, networking, and software. Customers place orders for complete systems, not just chips. Etched claims they deliver more tokens per dollar and per watt for dense models, sparse MoEs, diffusion models, and more. - **Software Stack**: Includes compiler and runtime optimizations built by a team with deep experience (former Apache TVM developer, ex-Google TPU software lead). ## Market Standing - **Valuation**: $5 billion post-money valuation (as of December 2025 / disclosed June 2026) - **Key Metric**: $1 billion in contract orders (booked) for its systems; total funding of $800M (including an unannounced $500M round closed Dec 2025 led by Stripes) - **Notable Investors**: Stripes (lead), VentureTech Alliance, Jane Street, Hudson River Trading, Two Sigma, Ribbit Capital. Angel investors include Andrej Karpathy, Geoffrey Hinton, Fei-Fei Li, Arthur Mensch, Scott Wu, Stanley Druckenmiller, Peter Thiel. Earlier backers: Positive Sum, Primary Venture Partners. - **Growth Signals**: - Headcount: 258 employees (as of mid-2026), up 141% year-over-year - 100+ active job postings across engineering, operations, and business functions - $500M raise in late 2025; first chip manufactured by TSMC in 2025 and now being tested with customers - Talent sources include Google (21), Apple (17), NVIDIA (16), Tesla (11), Intel (10), AMD (5) ## Competitive Advantages - **Transformer-specific architecture**: Unlike GPUs (which are general-purpose), Etched’s chip is hardwired only for transformer operations, enabling drastically lower cost and latency for today’s dominant AI model architecture. - **Full-stack system play**: By selling entire inference clusters (chip + rack + software), Etched captures more value and delivers a turnkey solution competitive with NVIDIA’s DGX/HGX systems. - **Deeply experienced leadership**: - CEO Gavin Uberti (Harvard math researcher, AI compiler expert, Apache TVM contributor) - President Robert Wachen (co-founded Prod AI incubator; Thiel Fellow) - VP of Platform (ex-NVIDIA 22 years, built HGX/DGX systems) - VP of Software (ex-Google DeepMind, lead TPU v1–v5 software) - Chief Architect Saptadeep Pal (former Auradine co-founder, chiplet expert) - VP of Hardware Engineering Ajat Hukkoo (ex-Cypress CTO, shipped >$1B revenue products) ## Strategic Focus - **Scale manufacturing and customer deliveries**: With the first chip successfully fabricated, the company is now testing production systems and aims to fulfill $1B in pre-orders. - **Expand engineering talent**: Aggressively hiring across silicon design, validation, infrastructure, optics, and software to support volume ramp. - **Maintain technological lead**: Continue refining the ASIC for future transformer variants and MoE mixtures while building out a partner ecosystem. ## Why Work Here - **Mission-driven, high-impact engineering**: “Building the hardware for superintelligence” – the company is solving one of the hardest problems in compute (inference efficiency) with a focused team. - **Top-tier team and learning environment**: Colleagues from Google, NVIDIA, Apple, Tesla, Broadcom, and Intel; exposure to full-stack chip-to-system design. - **In-office culture**: All roles are in-office (Cupertino and San Jose, CA). The company emphasizes on-site collaboration for hardware development. Notable perks are not heavily advertised, but compensation is competitive for the AI hardware space (equity-heavy). - **Growth trajectory**: 141% headcount growth YoY, hundreds of open roles, and a $5B valuation signal strong backing and career acceleration potential. - **Intellectual challenge**: Work on chip simulation, RTL design, system validation, or software infrastructure for cutting-edge AI inference. ## Sources 1. [etched.com/careers](https://www.etched.com/careers) 2. [builtin.com/company/etched](https://builtin.com/company/etched) 3. [linkedin.com/company/etched-ai](https://www.linkedin.com/company/etched-ai) 4. [cbinsights.com/company/etched](https://www.cbinsights.com/company/etched) 5. [techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/](https://techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/) ## Other roles at Etched - [Mechanical Engineer](https://feeny.ai/job/mechanical-engineer-etched-san-jose-42w9x3hmtqtj) — San Jose, CA - [Internal Acceleration, Research Engineer (Production)](https://feeny.ai/job/internal-acceleration-research-engineer-production-etched-san-jose-sqbyj2amhpjg) — San Jose, CA - [Internal Acceleration, Research Engineer (Hardware)](https://feeny.ai/job/internal-acceleration-research-engineer-hardware-etched-san-jose-tj3zyra40ktt) — San Jose, CA - [Internal Acceleration, Research Engineer (ASIC)](https://feeny.ai/job/internal-acceleration-research-engineer-asic-etched-san-jose-b9edwhnn0z7v) — San Jose, CA - [Internal Acceleration, Engineer (Special Projects)](https://feeny.ai/job/internal-acceleration-engineer-special-projects-etched-san-jose-1dwjbp016bhc) — San Jose, CA - [Internal Acceleration, Engineer (Production)](https://feeny.ai/job/internal-acceleration-engineer-production-etched-san-jose-a54mtqn5e9zy) — San Jose, CA - [Internal Acceleration, Engineer (Hardware)](https://feeny.ai/job/internal-acceleration-engineer-hardware-etched-san-jose-w98ba6ngtm3d) — San Jose, CA - [Internal Acceleration, Engineer (ASIC)](https://feeny.ai/job/internal-acceleration-engineer-asic-etched-san-jose-vknbkj44wrzn) — San Jose, CA - [Internal Acceleration, Research Engineer (Kernels)](https://feeny.ai/job/internal-acceleration-research-engineer-kernels-etched-san-jose-mvmvzpbtyfg3) — San Jose, CA - [Internal Acceleration, Engineer (Kernels)](https://feeny.ai/job/internal-acceleration-engineer-kernels-etched-san-jose-x8xw3xpxxpzr) — San Jose, CA