---
title: 'Digital - ASIC Design Automation Engineer at Eliyan'
canonical: 'https://feeny.ai/job/digital-asic-design-automation-engineer-eliyan-bay-area-vancouver-canada-zrevr29k1a32'
type: 'job'
last_seen: '2026-09-14'
---

# Digital - ASIC Design Automation Engineer at Eliyan

- **Company:** Eliyan
- **Location:** Bay Area / Vancouver, Canada / Toronto, Canada
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-05-13
- **Last confirmed live:** 2026-09-14
- **Apply:** https://jobs.lever.co/eliyan/fa0363c5-d4b9-4acb-9f78-6895db7ed24a

## Job description

AI-Augmented Design Flows · CI/CD for RTL · Lint / CDC / Synthesis Automation

## ABOUT THE ROLE

Eliyan is the chiplet interconnect pioneer behind NuLink, the industry's most efficient chiplet-to-chiplet PHY technology. With Series C funding from leading hyperscalers and AI infrastructure providers, we are scaling our digital design organization to support multiple concurrent IP programs across advanced process nodes. Here is the honest version of this job. Our digital designers spend part of every week doing work a machine should be doing: re-running lint and CDC by hand, reading thousands of violations to find the twenty that matter, chasing down which synthesis run regressed QoR, and manually assembling the evidence that a branch is clean enough to promote to release. Your job is to make that work disappear. You will own our Jenkins-based design flow infrastructure end to end and build the AI layer on top of it: agent-driven triage that filters lint and CDC noise down to the real issues, and automated pull requests that arrive pre-organized so a designer reviews a decision instead of excavating a log. The team is small enough that tooling you ship on Monday changes how it works on Tuesday.  MUST BE WILLING TO WORK ONSITE - M-F

## KEY RESPONSIBILITIES

Flow Automation and Quality Gates, and Release Promotion

- Own the Jenkins-based CI for RTL quality across active design programs: lint, CDC, RDC, elaboration, synthesis, and STA. Optimize for turnaround time, not only coverage.
- Build the dev-to-release promotion pipeline: automated gating that qualifies a branch on clean runs and produces the handoff evidence, so promotion becomes a button rather than a checklist.
- Build synthesis and timing result tracking: per-project dashboards that make QoR regressions obvious and attributable to the commit that caused them.
- Own the front-end release methodology: release criteria, handoff checkpoints, cross-team gating, and waiver management across lint and CDC tools.

AI-Augmented Tooling

- Build agent-driven violation triage: LLM pipelines that classify lint and CDC output, suppress known-benign patterns, cluster related violations, and surface the real ones with context.
- Build automated pull requests that arrive with violations already filtered, grouped, and annotated, turning a triage session into a review.
- Implement spec-to-RTL consistency checking using LLM-driven diff and review pipelines, plus CI integrated documentation generation.
- Own evaluation and guardrails: benchmark output quality, measure false-negative rates against real violation data, and set the guardrails the team can trust.

## MINIMUM QUALIFICATIONS

- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 3+ years building automation, CI/CD, or engineering tooling in a hardware, EDA, or infrastructure environment.
- Strong Python, plus Tcl, shell scripting, Git, Linux, and Makefiles. You are comfortable owning a codebase, not only writing scripts.
- Hands-on Jenkins (or GitLab CI / GitHub Actions) at a level where you have debugged and rearchitected a pipeline, not only used one.
- Working knowledge of the RTL front-end flow and SystemVerilog — enough to read lint and CDC output and reason about which violations matter.
- Practical experience with LLM APIs or agent frameworks (Anthropic Claude, OpenAI, or equivalent), applied to something real that other people used.
- Strong technical writing, and authorization to work in the United States or Canada as applicable to the office location; sponsorship may be considered for exceptional candidates.
- On-site Monday through Friday at our Bay Area, Vancouver, or Toronto office. This role is not remote.

## PREFERRED QUALIFICATIONS

- Familiarity with industry-standard EDA tools (Synopsys VCS, Verdi, PrimeTime, Design Compiler; Cadence Genus; Spyglass; Questa; JasperGold).
- Background in data engineering or ML systems: evaluation harnesses, retrieval pipelines, or production inference.
- Exposure to digital design, SoC, PHY, SerDes, or chiplet interconnect domains.
- Open-source contributions to design automation, hardware verification, or developer tooling.

## A NOTE ON FIT

The AI work here is applied engineering, not research: prompt and agent design, evaluation harnesses, and the plumbing that makes a pipeline reliable the night before a tapeout deadline. If your goal is to train models or publish, this is not the right role. The role can also grow toward digital design ownership over time, with senior mentorship available.

## HOW TO APPLY

Share resume PLUS tell us about one tool you built and what it replaced.

## About Eliyan

## Company Overview
- **One-liner**: Eliyan develops high-bandwidth, low-power chiplet interconnect technology (NuLink) that solves data bottlenecks in AI and data center chips.
- **Entity Type**: Private (Series C-II)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2021
- **Founders**: Ramin Farjadrad (CEO), Syrus Ziai (VP Engineering), Patrick Soheili (Chief Strategy & Business Officer)

## Core Business
- Primary industry: Semiconductor Manufacturing (chiplet interconnect IP and PHY silicon)
- Target customers: B2B – companies building custom AI chips (hyperscalers, chip designers, networking firms)
- Mission: “Revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.”

## Products & Services
- **[NuLink™ D2D PHY](https://eliyan.com/about/)**: Die-to-die interconnect PHY supporting industry standards (BoW and UCIe) and proprietary simultaneous-bidirectional (SBD) technology. Delivers 4× the bandwidth and 2× the power efficiency of alternatives in advanced or standard packaging, with bump pitches from 40–130 microns.
- **[NuLink™-XD](https://linkedin.com/company/eliyan-corporation)**: A new class of power-reach configurable 224G PAM4 SerDes for chip-to-chip and chip-to-module applications, targeting the lowest-power electro-optical modules for AI scale-up networks. Up to 40% lower power than competing solutions.

## Market Standing
- **Valuation**: $1 billion (as of July 2026 Series C)
- **Annual Revenue**: $3.5 million (2025); forecasts hundreds of millions by end of 2027 [reuters.com](https://www.cbinsights.com/company/eliyan)
- **Total Funding**: $295 million (conflicting reports: other sources state $150M total); includes $145M Series C led by Seligman Ventures (July 2026), $60M Series B led by Samsung Catalyst Fund and Tiger Global (March 2024), $40M Series A led by Tracker Capital (Nov 2022).
- **Notable Investors/Partners**: Seligman Ventures (board seat for Umesh Padval), Cisco Systems, Lumentum, Samsung Catalyst Fund, Tiger Global Management, Tracker Capital, VentureTech Alliance.
- **Growth Signals**: Headcount of 73 employees with +6.7% monthly growth; 21 active job postings (quarterly trend +2,000%); expects to start chiplet shipments in 2026; expanding across 6 countries (US, Germany, Netherlands, Canada, India, Israel).

## Competitive Advantages
- Breakthrough die-to-die interconnect architecture (invented by founder Ramin Farjadrad in 2016) that achieves 4× bandwidth and 2× power efficiency versus competing IP.
- Works with standard packaging (wide range of bump pitches), reducing cost and complexity for chip designers.
- Independent alternative to Broadcom/Marvell in the chiplet interconnect space, giving custom AI chip makers a neutral, high-performance option.

## Strategic Focus
- Solving the growing data-movement bottleneck in AI compute (GPUs often idle 30–40% waiting for data).
- Scaling NuLink and NuLink-XD platforms to support both chip-to-chip and chip-to-module applications for next-generation AI infrastructure.
- Ramping chiplet production and licensing revenue, targeting hundreds of millions in sales by 2027.

## Why Work Here
- On-site culture with offices in Santa Clara (HQ), Vancouver (BC), and other global locations; no remote/hybrid mentioned.
- Engineering-heavy team (54% technical roles) with a fast-paced startup environment and deep expertise from companies like Marvell, Intel, AMD, and Synopsys.
- Opportunity to work on cutting-edge semiconductor interconnect technology that directly impacts AI performance.
- Active hiring across digital design, verification, DFT, physical design, optical engineering, and program management.

## Sources
1. [eliyan.com/about](https://eliyan.com/about/)
2. [jobs.lever.co/eliyan](https://jobs.lever.co/eliyan)
3. [linkedin.com/company/eliyan-corporation](https://linkedin.com/company/eliyan-corporation)
4. [cbinsights.com/company/eliyan](https://www.cbinsights.com/company/eliyan)
5. [reuters.com (via CNA)](https://www.cbinsights.com/company/eliyan) (Note: embedded Reuters article on CB Insights page)
6. [eliyan.com/careers](https://eliyan.com/careers/)

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