---
title: 'Digital - ASIC Design Automation & Integration Engineer at Eliyan'
canonical: 'https://feeny.ai/job/digital-asic-design-automation-integration-engineer-eliyan-san-francisco-bay-zrevr29k1a32'
type: 'job'
last_seen: '2026-11-02'
---

# Digital - ASIC Design Automation & Integration Engineer at Eliyan

- **Company:** Eliyan
- **Location:** San Francisco Bay Area, CA / Vancouver, Canada / Toronto, Canada
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-05-13
- **Last confirmed live:** 2026-11-02
- **Apply:** https://jobs.lever.co/eliyan/fa0363c5-d4b9-4acb-9f78-6895db7ed24a

## Job description

Lint / CDC / Synthesis Quality · IP & Chip Integration · AI-Augmented Design Flows · CI/CD for RTL On-Site Monday-Friday - Bay Area, CA / Vancouver, BC / Toronto, ON Full-Time - Equity Participation - Comprehensive Benefits

## ABOUT THE ROLE

Eliyan is the chiplet interconnect pioneer behind NuLink, the industry's most efficient chiplet-to-chiplet PHY technology. With Series C funding from leading hyperscalers and AI infrastructure providers, we are scaling our digital design organization to support multiple concurrent IP programs across advanced process nodes. We are looking for an engineer who can own the intersection of design quality, automation, and design integration. In this role you will define and enforce signoff criteria for lint, CDC, and synthesis across all active programs, build the waiver management and tracking infrastructure, and develop AI-augmented tooling that turns thousands of tool violations into actionable, designer-ready reviews. You will report into the digital design team and work directly alongside RTL designers. Design quality and automation are the core of this role. IP and chip-level integration ownership is scope you can grow into as you ramp — we're looking for someone who wants it.

## KEY RESPONSIBILITIES

Design Quality & Signoff

- Define and maintain lint, CDC, and synthesis elaboration signoff criteria across all active design programs.
- Build and own the waiver management system — structured flow with owner attribution, justification, expiration, and audit trail.
- Analyze synthesis results for area, timing, and power regressions; trace QoR anomalies to specific RTL changes.
- Collaborate with project design leads to develop and maintain project-specific rule decks, synthesis constraints, and signoff checklists.

IP & Chip Integration

- Own RTL integration of digital IP into PHY and chip-level hierarchies — instantiation, parameterization, hierarchy assembly, and interface consistency across IP boundaries.
- Build automated integration checks: top-level connectivity, tie-off and floating-input detection, clock and reset connectivity, and interface consistency between IP and SoC.
- Automate register map and interface collateral generation (e.g. PeakRDL, IP-XACT) and keep RTL, firmware headers, and documentation in sync.
- Own IP release packaging and delivery — versioned collateral, dependency tracking, and reproducible builds from a tagged release, with handoff evidence for internal and customer deliveries.
- Run lint, CDC, RDC, and elaboration at full-chip scope, and drive cross-IP and integration-level findings to closure with the owning designers.

Flow Automation and CIC

- Own the Jenkins-based CI pipeline for RTL quality: lint, CDC, RDC, elaboration, synthesis, and STA.
- Build the dev-to-release promotion pipeline with automated gating, clean-run qualification, and handoff evidence generation.
- Develop per-project dashboards for QoR tracking, regression visibility, and release readiness.

AI-Augmented Tooling

- Develop LLM-based violation triage pipelines that classify lint and CDC output, suppress known-benign patterns, and surface real issues with context.
- Build automated pull requests with violations pre-filtered, grouped, and annotated for designer review.
- Implement spec-to-RTL consistency checking and CI-integrated documentation generation using LLM-driven pipelines.
- Benchmark AI output quality, measure false-negative rates, and establish guardrails the design team can trust.

## MINIMUM REQUIREMENTS

- Bachelors, Masters or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 5+ years in ASIC or SoC design or design automation, with hands-on experience running and analyzing lint, CDC, or synthesis tools.
- Familiarity with Lint/CDC/RDC tools like VC SpyGlass or QuestaLint/CDC.
- Familiarity with Synthesis tools like Genus or Fusion Compiler.
- Working knowledge of SystemVerilog and the RTL front-end flow — able to read violations, assess severity, and disposition findings.
- Proficiency in Python, Tcl, shell scripting, Git, Linux, and Makefiles.
- Experience building and maintaining CI/CD pipelines (Jenkins, GitLab CI, or GitHub Actions).
- Authorization to work in the United States or Canada; visa sponsorship may be considered for exceptional candidates.
- On-site Monday through Friday at our Bay Area, Vancouver, or Toronto office.

## PREFERRED QUALIFICATIONS

- Experience building waiver management systems, violation databases, or design quality dashboards.
- Experience with register map automation and IP packaging standards (PeakRDL, SystemRDL, or IP-XACT).
- Knowledge of UPF and power intent.
- Knowledge of Static Timing Analysis.
- Practical experience with LLM APIs or agent frameworks (e.g., Anthropic Claude, OpenAI) applied in a production or team-facing context.
- Hands-on experience integrating and releasing digital IP — hierarchy assembly, connectivity closure, versioned collateral, and handoff to internal or external consumers.
- Exposure to PHY, SerDes, die-to-die interconnect, or chiplet-based SoC design.
- Open-source contributions to design automation, hardware verification, or developer tooling.

## About Eliyan

## Company Overview
- **One-liner**: Eliyan develops high-bandwidth, low-power chiplet interconnect technology (NuLink) that solves data bottlenecks in AI and data center chips.
- **Entity Type**: Private (Series C-II)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2021
- **Founders**: Ramin Farjadrad (CEO), Syrus Ziai (VP Engineering), Patrick Soheili (Chief Strategy & Business Officer)

## Core Business
- Primary industry: Semiconductor Manufacturing (chiplet interconnect IP and PHY silicon)
- Target customers: B2B – companies building custom AI chips (hyperscalers, chip designers, networking firms)
- Mission: “Revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.”

## Products & Services
- **[NuLink™ D2D PHY](https://eliyan.com/about/)**: Die-to-die interconnect PHY supporting industry standards (BoW and UCIe) and proprietary simultaneous-bidirectional (SBD) technology. Delivers 4× the bandwidth and 2× the power efficiency of alternatives in advanced or standard packaging, with bump pitches from 40–130 microns.
- **[NuLink™-XD](https://linkedin.com/company/eliyan-corporation)**: A new class of power-reach configurable 224G PAM4 SerDes for chip-to-chip and chip-to-module applications, targeting the lowest-power electro-optical modules for AI scale-up networks. Up to 40% lower power than competing solutions.

## Market Standing
- **Valuation**: $1 billion (as of July 2026 Series C)
- **Annual Revenue**: $3.5 million (2025); forecasts hundreds of millions by end of 2027 [reuters.com](https://www.cbinsights.com/company/eliyan)
- **Total Funding**: $295 million (conflicting reports: other sources state $150M total); includes $145M Series C led by Seligman Ventures (July 2026), $60M Series B led by Samsung Catalyst Fund and Tiger Global (March 2024), $40M Series A led by Tracker Capital (Nov 2022).
- **Notable Investors/Partners**: Seligman Ventures (board seat for Umesh Padval), Cisco Systems, Lumentum, Samsung Catalyst Fund, Tiger Global Management, Tracker Capital, VentureTech Alliance.
- **Growth Signals**: Headcount of 73 employees with +6.7% monthly growth; 21 active job postings (quarterly trend +2,000%); expects to start chiplet shipments in 2026; expanding across 6 countries (US, Germany, Netherlands, Canada, India, Israel).

## Competitive Advantages
- Breakthrough die-to-die interconnect architecture (invented by founder Ramin Farjadrad in 2016) that achieves 4× bandwidth and 2× power efficiency versus competing IP.
- Works with standard packaging (wide range of bump pitches), reducing cost and complexity for chip designers.
- Independent alternative to Broadcom/Marvell in the chiplet interconnect space, giving custom AI chip makers a neutral, high-performance option.

## Strategic Focus
- Solving the growing data-movement bottleneck in AI compute (GPUs often idle 30–40% waiting for data).
- Scaling NuLink and NuLink-XD platforms to support both chip-to-chip and chip-to-module applications for next-generation AI infrastructure.
- Ramping chiplet production and licensing revenue, targeting hundreds of millions in sales by 2027.

## Why Work Here
- On-site culture with offices in Santa Clara (HQ), Vancouver (BC), and other global locations; no remote/hybrid mentioned.
- Engineering-heavy team (54% technical roles) with a fast-paced startup environment and deep expertise from companies like Marvell, Intel, AMD, and Synopsys.
- Opportunity to work on cutting-edge semiconductor interconnect technology that directly impacts AI performance.
- Active hiring across digital design, verification, DFT, physical design, optical engineering, and program management.

## Sources
1. [eliyan.com/about](https://eliyan.com/about/)
2. [jobs.lever.co/eliyan](https://jobs.lever.co/eliyan)
3. [linkedin.com/company/eliyan-corporation](https://linkedin.com/company/eliyan-corporation)
4. [cbinsights.com/company/eliyan](https://www.cbinsights.com/company/eliyan)
5. [reuters.com (via CNA)](https://www.cbinsights.com/company/eliyan) (Note: embedded Reuters article on CB Insights page)
6. [eliyan.com/careers](https://eliyan.com/careers/)

## Other roles at Eliyan

- [Program Management - Principal / Sr. Principal Technical Program Manager – IP, ASIC & Chiplet Platforms](https://feeny.ai/job/program-management-principal-sr-principal-technical-program-manager-ip-asic-29s06vbpaq89) — San Francisco Bay Area, CA
- [Silicon Validation, Test & Characterization Engineer (title will reflect experience)](https://feeny.ai/job/silicon-validation-test-characterization-engineer-title-will-reflect-experience-9n726paagrw8) — San Francisco Bay Area, CA
- [DV - Staff (+) Verification Engineer -  AMS modeling](https://feeny.ai/job/dv-staff-verification-engineer-ams-modeling-eliyan-san-francisco-bay-area-27k4khnvjx3y) — San Francisco Bay Area, CA / Vancouver, Canada / Toronto, Canada
- [PD - Sr Staff - Physical Verification Lead | Signoff & DRC](https://feeny.ai/job/pd-sr-staff-physical-verification-lead-signoff-drc-eliyan-san-francisco-bay-area-jmkanxqtq810) — San Francisco Bay Area, CA
- [PD - Sr Staff  — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |](https://feeny.ai/job/pd-sr-staff-cad-design-methodology-rtl-to-gdsii-flow-advanced-node-methodology-gtnhek1texp8) — San Francisco Bay Area, CA
- [DV - Principal Digital Verification Engineer](https://feeny.ai/job/dv-principal-digital-verification-engineer-eliyan-vancouver-bc-or-bay-area-jttvf7k0jdc6) — Vancouver Bc OR Bay Area, CA
- [DV - Staff Verification Engineer -  Serdes](https://feeny.ai/job/dv-staff-verification-engineer-serdes-eliyan-san-francisco-bay-area-3sesn9ej7d97) — San Francisco Bay Area, CA / Vancouver, Canada / Toronto, Canada
- [Photonics IC Validation and Characterization Engineer (title will reflect experience)](https://feeny.ai/job/photonics-ic-validation-and-characterization-engineer-title-will-reflect-kj77ht3q4rp9) — San Francisco Bay Area, CA
- [Digital - SerDes Digital Design Lead](https://feeny.ai/job/digital-serdes-digital-design-lead-eliyan-san-francisco-bay-area-6mznhxayfytd) — San Francisco Bay Area, CA
- [DV - Director of Design Verification](https://feeny.ai/job/dv-director-of-design-verification-eliyan-san-francisco-bay-area-d0rz6whbjstf) — San Francisco Bay Area, CA