---
title: 'Digital Design Manager at Astera Labs'
canonical: 'https://feeny.ai/job/digital-design-manager-astera-labs-toronto-crzqy4ghxbsq'
type: 'job'
last_seen: '2026-09-18'
---

# Digital Design Manager at Astera Labs

- **Company:** Astera Labs
- **Location:** Toronto, Canada
- **Posted:** 2026-09-15
- **Last confirmed live:** 2026-09-18
- **Apply:** https://job-boards.greenhouse.io/asteralabs/jobs/4731807005

## Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/).

## Role Overview

This role will lead day-to-day DFT architecture and execution for Astera Labs' signal-conditioning products, helping deliver highly testable, high-quality silicon for rack-scale AI infrastructure. You will partner with design, verification, physical design, packaging, product engineering, and manufacturing teams to improve coverage, yield, diagnostics, and production readiness across advanced multi-die products.

As Astera Labs scales its purpose-built connectivity platform, you will help establish practical DFT methods for high-speed PCIe and Ethernet signal-conditioning products, with a strong focus on SerDes physical-layer performance, signal integrity, and production robustness. The role offers hands-on technical ownership, opportunities to mentor engineers, and direct influence on products that keep next-generation AI systems connected, observable, and reliable.

## Key Responsibilities

- DFT Architecture & Planning

- Define DFT plans for signal-conditioning products supporting high-speed PCIe and Ethernet connectivity and advanced multi-die packaging configurations.

- Develop test-access, coverage, observability, and diagnostic strategies for die-to-die interfaces, interposers, and package-level integration.

- Partner with design and physical design teams to balance DFT area, timing, routing, and manufacturability.

- DFT Implementation & Silicon Readiness

- Drive scan insertion, ATPG, compression, MBIST, LBIST, JTAG/IJTAG, and high-speed SerDes BIST requirements.

- Establish coverage targets and review ATPG results, pattern quality, test time, and ATE cost.

- Support tape-out, wafer sort, packaged-device test, silicon bring-up, characterization, and production ramp.

- Quality, Yield & Diagnostics

- Collaborate with product, manufacturing, assembly, and test engineering on yield learning, failure analysis, and root-cause resolution.

- Develop pre-bond, post-bond, and package-level test approaches for known-good-die screening and advanced packaging.

- Improve diagnostic capabilities for silicon, package, and system-level issues.

- Technical Leadership & Collaboration

- Mentor DFT engineers and coordinate execution across product development milestones.

- Partner with OSATs, ATE vendors, packaging partners, and internal stakeholders to resolve technical issues and maintain schedules.

- Communicate risks, trade-offs, and recommendations clearly to cross-functional teams.

## Basic Qualifications

- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.

- 10-15 years of experience in Digital Design engineering or related semiconductor design and test work.

- Hands-on experience with scan, ATPG, compression, MBIST, LBIST, JTAG, and/or IJTAG methodologies.

- Understanding of the ASIC design flow from RTL through GDS and DFT signoff.

- Experience with DFT EDA tools such as Synopsys DFT Compiler, TetraMAX, DFTMAX, Siemens Tessent, or equivalent.

- Understanding of high-speed signal conditioning, SerDes physical-layer behavior, signal integrity, die-to-die connectivity, or advanced packaging test requirements.

## Preferred Qualifications

- Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.

- Experience with 2.5D or 3D integration, silicon interposers, TSVs, hybrid bonding, micro-bumps, chiplets, or known-good-die strategies.

- Knowledge of IEEE 1838, IEEE 1149.1, IEEE 1687, and relevant JEDEC standards for multi-die testing.

- Experience with PCIe, Ethernet, UALink, and high-speed SerDes physical-layer validation or test.

- Familiarity with ATE platforms, wafer probe, OSAT engagement, production test economics, and yield analysis.

Salary range is CAD $198,000 to CAD $220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## About Astera Labs

## Company Overview
- **One-liner**: Astera Labs designs and delivers semiconductor-based connectivity solutions purpose-built to unleash the full potential of cloud and AI infrastructure.
- **Entity Type**: Public (Nasdaq: ALAB)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2017
- **Founders**: Jitendra Mohan, Sanjay Gajendra, Casey Morrison

## Core Business
- **Primary industry**: Semiconductor manufacturing / AI infrastructure connectivity
- **Target customers**: B2B, primarily hyperscale cloud providers and system OEMs (e.g., NVIDIA, AMD, Intel)
- **Mission statement**: To innovate, design, and deliver semiconductor-based connectivity solutions that are purpose-built to unleash the full potential of cloud and AI infrastructure.

## Products & Services
- **Aries PCIe®/CXL™ Smart DSP Retimers**: Silicon ICs, boards, and modules that digitally recover degraded high-speed signals to extend reach and enable higher PCIe/CXL data bandwidth between compute, storage, and network controllers.
- **Taurus Ethernet Smart Cable Modules™**: Hardware modules that increase network connectivity bandwidth between servers and switches over copper media, removing rack-level Ethernet bottlenecks.
- **Leo CXL Memory Connectivity Controllers**: ICs and boards that expand, share, and pool DRAM memory to overcome processor memory bandwidth bottlenecks for AI workloads.
- **Scorpio Smart Fabric Switches**: A family of PCIe 6 fabric switches ranging from 32 to 320 lanes, including the new 320-lane Scorpio X-Series Fabric Switch for AI scale-up fabrics.
- **COSMOS Software Suite**: A connectivity system management and optimization software that enables configuration, monitoring, troubleshooting, and predictive analytics for all Astera Labs products.

## Market Standing
- **Market Cap**: ~$11.6 billion (as of mid-2026)
- **Key Metric - Revenue**: $35 million (annual, reported)
- **Key Metric - Operating Income**: $173.4 million (2025)
- **Key Metric - Net Income**: $219.1 million (2025)
- **Total Funding**: ~$810.75 million (pre-IPO), with Series C ($50M, led by Fidelity) and Series D ($150M, led by Fidelity)
- **IPO Date**: March 20, 2024
- **Notable Investors/Partners**: Fidelity, NVIDIA, Advanced Micro Devices, Intel, major hyperscalers
- **Growth Signals**: 92% YoY headcount growth (675 employees); 144 active job postings (+260% YoY); expanded Taiwan operations with a new Cloud-Scale Interop Lab in 2026; shipping millions of devices across all major hyperscalers; 300+ design wins.

## Competitive Advantages
- **First-to-market innovation**: Pioneered first-to-market PCIe, Ethernet, and CXL connectivity products.
- **Patented software-defined platform approach**: Differentiates via a platform that combines silicon hardware with embedded COSMOS software, enabling flexibility, observability, and predictive analytics.
- **Deep hyperscaler relationships**: Trusted partner to the world’s largest cloud providers, with proven interoperability validated in their own Cloud-Scale Interop Lab.
- **Broad product portfolio**: Covers PCIe retimers, Ethernet cable modules, CXL memory controllers, and fabric switches—addressing the full spectrum of AI connectivity bottlenecks.
- **Strong IP and engineering talent**: 443 employees in technical roles; talent sourced from Intel (65), Marvell (37), Texas Instruments (40), AMD (22), and NVIDIA.

## Strategic Focus
- **Scaling AI infrastructure**: Expanding product portfolio and global footprint (12 countries) to meet surging demand for rack-scale AI.
- **Open standards leadership**: All products are grounded in open standards (PCIe, CXL, Ethernet), ensuring interoperability and broad adoption.
- **Taiwan expansion**: Growing engineering presence and Interop Lab in Taiwan to strengthen integration with leading AI platform providers and system manufacturers.
- **Continued innovation**: Shipping the new 320-lane Scorpio X-Series Fabric Switch and expanding the COSMOS software suite for fleet-level management and optimization.

## Why Work Here
- **Culture**: Described as collaborative, ownership-driven, and focused on solving complex problems together. The company emphasizes diversity and inclusion as drivers of creativity and innovation.
- **Growth**: Astera Labs supports non-linear career growth—employees can deepen expertise (“scale up”) or broaden into new areas (“scale out”). 92% YoY headcount growth signals rapid expansion and opportunity.
- **Remote/Hybrid**: Not explicitly stated, but global operations across 12 countries (including India, Canada, Israel, Taiwan, Vietnam) suggest a flexible, distributed work model.
- **Benefits**: Competitive medical, dental, and vision plans; flexible time off; family planning and parental leave; 401K and retirement plans.
- **Engineering culture**: Strong focus on cutting-edge semiconductor and AI infrastructure technology. High concentration of senior (24%) and specialist (19%) talent. Active internship and new graduate programs.
- **Employee ratings**: 4.5/5.0 on LinkedIn (124 reviews), with high marks for compensation (4.6), culture (4.4), and career development (4.4).

## Sources
1. [Astera Labs Careers Page](https://www.asteralabs.com/careers/)
2. [Astera Labs Official Website](https://www.asteralabs.com/)
3. [Astera Labs LinkedIn](https://www.linkedin.com/company/astera-labs)
4. [Astera Labs Products Page](https://www.asteralabs.com/products/)
5. [Astera Labs S-1 Filing (SEC)](https://ir.asteralabs.com/static-files/7103a4cb-aa6b-4f11-a4b0-f179cd4c5bee)

## Other roles at Astera Labs

- [Template Job](https://feeny.ai/job/template-job-astera-labs-san-jose-california-hsrq2w5dnj4b) — San Jose California, United States
- [Principal Signal and Power Integrity Engineer](https://feeny.ai/job/principal-signal-and-power-integrity-engineer-astera-labs-shanghai-z3528r4p4kz5) — Shanghai, China
- [Manager, Digital Design](https://feeny.ai/job/manager-digital-design-astera-labs-san-jose-california-v98047j0w79e) — San Jose California, United States
- [Principal Logic Design Engineer - UALink IP/Subsystem](https://feeny.ai/job/principal-logic-design-engineer-ualink-ip-subsystem-astera-labs-bengaluru-9shc23w9csza) — Bengaluru, India
- [Lead Logic Design - PCIE IP/Subsystem Engineer](https://feeny.ai/job/lead-logic-design-pcie-ip-subsystem-engineer-astera-labs-bengaluru-kwd80z6s6yng) — Bengaluru, India
- [Senior System Validation Engineer](https://feeny.ai/job/senior-system-validation-engineer-astera-labs-tel-aviv-yafo-7grrjpfc0rdd) — Tel Aviv-Yafo, Israel
- [Tech Lead, STA](https://feeny.ai/job/tech-lead-sta-astera-labs-hyderabad-b4sgrwnz1ybc) — Hyderabad, India
- [Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet](https://feeny.ai/job/principal-senior-principal-design-verification-engineer-cxl-pcie-ethernet-yzpz44j7h93t) — San Jose California, United States
- [Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet](https://feeny.ai/job/principal-senior-principal-design-verification-engineer-cxl-pcie-ethernet-0jtpt6yr55yd) — Taipei, Taiwan
- [Principal/ Sr Principal Digital Design Engineer](https://feeny.ai/job/principal-sr-principal-digital-design-engineer-astera-labs-taipei-dda1w0n4a6jr) — Taipei, Taiwan