--- title: 'Director ASIC Technical Program Management at Astera Labs' canonical: 'https://feeny.ai/job/director-asic-technical-program-management-astera-labs-san-jose-xhb8x12hczwz' type: 'job' last_seen: '2026-10-16' --- # Director ASIC Technical Program Management at Astera Labs - **Company:** Astera Labs - **Location:** San Jose, CA - **Posted:** 2026-10-15 - **Last confirmed live:** 2026-10-16 - **Apply:** https://job-boards.greenhouse.io/asteralabs/jobs/4744234005 ## Job description Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/). ## Role Overview We are looking for a  Director ASIC Technical Program Management to join the PMO organization at Astera Labs, based in the USA. In this role, you will directly manage a team of Technical Program Managers (TPMs) located across the United States. You will be responsible for mentoring and developing your team, ensuring alignment on methodology, and maintaining full visibility into program status across the portfolio. While your primary focus is people leadership, you are expected to remain hands-on — stepping in to lead programs directly when the need arises. ## What You'll Do You will lead the US-based TPM team, which owns the cross-functional execution framework for advanced ASIC programs from early planning through production release. Your team drives milestone planning, dependency management, execution reviews, decision-making forums, and risk mitigation across multiple engineering disciplines. You will be accountable for program readiness at key gates — including tapeout, power-on, and production release — and will set the standard for how execution is tracked, communicated, and acted upon across the organization. A core part of your role is bringing consistency and clarity to program status reporting. You will work closely with executive leadership and the PLM team to enable fast, well-informed decision-making, and to ensure that all functions have transparent, real-time visibility into program health and priorities. You will partner directly with external partners and customers as a senior representative of the program. ## Why This Role Matters This is a high-impact leadership position for someone who thrives in a fast-paced, ambiguous environment. You will be expected to drive accountability, manage complexity across multiple concurrent programs, and build scalable execution practices that strengthen the team's ability to deliver world-class silicon. ## Your Background Program Ownership & Execution You have owned the full ASIC program lifecycle end-to-end — from architecture and RTL through physical design, tapeout, validation, customer sampling, qualification, and release to manufacturing. You are comfortable serving as the single point of accountability for assigned programs, driving planning, scheduling, budgeting, resource allocation, and risk management with minimal oversight. Cross-Functional Leadership & Issue Resolution You have a strong track record leading cross-functional teams spanning design, validation, product, test, firmware, software, and operations. When complex pre-silicon or post-silicon issues arise, you bring the technical judgment needed to cut through ambiguity, align the right people, and drive resolution quickly. Stakeholder Management & Alignment You are skilled at navigating scope, schedule, and cost trade-offs, and at communicating program status, risks, and decisions clearly to executives and stakeholders at all levels. You know how to champion rigorous execution while keeping engineering delivery tightly aligned with business priorities and customer commitments. People Leadership Prior experience managing TPMs or leading technical teams is a strong plus. Candidates with a proven people management background — including hiring, mentoring, and developing technical contributors — will be given preference. That said, we recognize that great leaders are built in different ways: candidates who bring deep, hands-on experience delivering multiple ASIC programs from concept through production, combined with strong coaching instincts, clear communication, and the ability to inspire and align a team, are encouraged to apply. If you have the technical credibility and the people skills, we want to hear from you. ## Basic Qualifications - BS or MS in Electrical, Electronics, or Computer Engineering - 15+ years of ASIC product development experience in a semiconductor environment - Strong understanding of ASIC development flows, with hands-on experience in RTL, DSP, or Physical - Design Experience delivering ASICs in advanced nodes - Proven ability to lead in a matrixed, high-pressure environment - Strong program management and Leadership skill Salary range is $210,000 to $275,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. ## About Astera Labs ## Company Overview - **One-liner**: Astera Labs designs and delivers semiconductor-based connectivity solutions purpose-built to unleash the full potential of cloud and AI infrastructure. - **Entity Type**: Public (Nasdaq: ALAB) - **Headquarters**: Santa Clara, California, United States - **Founded**: 2017 - **Founders**: Jitendra Mohan, Sanjay Gajendra, Casey Morrison ## Core Business - **Primary industry**: Semiconductor manufacturing / AI infrastructure connectivity - **Target customers**: B2B, primarily hyperscale cloud providers and system OEMs (e.g., NVIDIA, AMD, Intel) - **Mission statement**: To innovate, design, and deliver semiconductor-based connectivity solutions that are purpose-built to unleash the full potential of cloud and AI infrastructure. ## Products & Services - **Aries PCIe®/CXL™ Smart DSP Retimers**: Silicon ICs, boards, and modules that digitally recover degraded high-speed signals to extend reach and enable higher PCIe/CXL data bandwidth between compute, storage, and network controllers. - **Taurus Ethernet Smart Cable Modules™**: Hardware modules that increase network connectivity bandwidth between servers and switches over copper media, removing rack-level Ethernet bottlenecks. - **Leo CXL Memory Connectivity Controllers**: ICs and boards that expand, share, and pool DRAM memory to overcome processor memory bandwidth bottlenecks for AI workloads. - **Scorpio Smart Fabric Switches**: A family of PCIe 6 fabric switches ranging from 32 to 320 lanes, including the new 320-lane Scorpio X-Series Fabric Switch for AI scale-up fabrics. - **COSMOS Software Suite**: A connectivity system management and optimization software that enables configuration, monitoring, troubleshooting, and predictive analytics for all Astera Labs products. ## Market Standing - **Market Cap**: ~$11.6 billion (as of mid-2026) - **Key Metric - Revenue**: $35 million (annual, reported) - **Key Metric - Operating Income**: $173.4 million (2025) - **Key Metric - Net Income**: $219.1 million (2025) - **Total Funding**: ~$810.75 million (pre-IPO), with Series C ($50M, led by Fidelity) and Series D ($150M, led by Fidelity) - **IPO Date**: March 20, 2024 - **Notable Investors/Partners**: Fidelity, NVIDIA, Advanced Micro Devices, Intel, major hyperscalers - **Growth Signals**: 92% YoY headcount growth (675 employees); 144 active job postings (+260% YoY); expanded Taiwan operations with a new Cloud-Scale Interop Lab in 2026; shipping millions of devices across all major hyperscalers; 300+ design wins. ## Competitive Advantages - **First-to-market innovation**: Pioneered first-to-market PCIe, Ethernet, and CXL connectivity products. - **Patented software-defined platform approach**: Differentiates via a platform that combines silicon hardware with embedded COSMOS software, enabling flexibility, observability, and predictive analytics. - **Deep hyperscaler relationships**: Trusted partner to the world’s largest cloud providers, with proven interoperability validated in their own Cloud-Scale Interop Lab. - **Broad product portfolio**: Covers PCIe retimers, Ethernet cable modules, CXL memory controllers, and fabric switches—addressing the full spectrum of AI connectivity bottlenecks. - **Strong IP and engineering talent**: 443 employees in technical roles; talent sourced from Intel (65), Marvell (37), Texas Instruments (40), AMD (22), and NVIDIA. ## Strategic Focus - **Scaling AI infrastructure**: Expanding product portfolio and global footprint (12 countries) to meet surging demand for rack-scale AI. - **Open standards leadership**: All products are grounded in open standards (PCIe, CXL, Ethernet), ensuring interoperability and broad adoption. - **Taiwan expansion**: Growing engineering presence and Interop Lab in Taiwan to strengthen integration with leading AI platform providers and system manufacturers. - **Continued innovation**: Shipping the new 320-lane Scorpio X-Series Fabric Switch and expanding the COSMOS software suite for fleet-level management and optimization. ## Why Work Here - **Culture**: Described as collaborative, ownership-driven, and focused on solving complex problems together. The company emphasizes diversity and inclusion as drivers of creativity and innovation. - **Growth**: Astera Labs supports non-linear career growth—employees can deepen expertise (“scale up”) or broaden into new areas (“scale out”). 92% YoY headcount growth signals rapid expansion and opportunity. - **Remote/Hybrid**: Not explicitly stated, but global operations across 12 countries (including India, Canada, Israel, Taiwan, Vietnam) suggest a flexible, distributed work model. - **Benefits**: Competitive medical, dental, and vision plans; flexible time off; family planning and parental leave; 401K and retirement plans. - **Engineering culture**: Strong focus on cutting-edge semiconductor and AI infrastructure technology. High concentration of senior (24%) and specialist (19%) talent. Active internship and new graduate programs. - **Employee ratings**: 4.5/5.0 on LinkedIn (124 reviews), with high marks for compensation (4.6), culture (4.4), and career development (4.4). ## Sources 1. [Astera Labs Careers Page](https://www.asteralabs.com/careers/) 2. [Astera Labs Official Website](https://www.asteralabs.com/) 3. [Astera Labs LinkedIn](https://www.linkedin.com/company/astera-labs) 4. [Astera Labs Products Page](https://www.asteralabs.com/products/) 5. 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