---
title: 'Director of Analog and Mixed-Signal IC Design at Neurophos'
canonical: 'https://feeny.ai/job/director-of-analog-and-mixed-signal-ic-design-neurophos-austin-3p5774p64xsn'
type: 'job'
last_seen: '2026-10-19'
---

# Director of Analog and Mixed-Signal IC Design at Neurophos

- **Company:** Neurophos
- **Location:** Austin, TX
- **Compensation:** $260k–$300k
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-10-02
- **Last confirmed live:** 2026-10-19
- **Apply:** https://jobs.ashbyhq.com/neurophos/86be4964-5ca0-4bcb-ae84-8bf06387d8b8

## Job description

## About Neurophos

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a [$110M Series A](https://www.neurophos.com/110m-raise) led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

Location: Austin, TX. Full-time onsite position. Reports To: VP of VLSI FLSA Status: Exempt

Position Overview Neurophos is seeking a Director of Analog and Mixed-Signal IC Design to build and lead the team responsible for the electronic circuits that drive, sense, and connect our optical processing unit. Our OPU depends on dense, energy-efficient electronics operating in close partnership with photonics: high-speed data converters and drivers that move information into and out of the optical domain, low-power analog front ends that read out the photonic signals, clocking and power management that keep the system stable, and high-bandwidth links that connect it to the rest of the data center. In this role, you will build and run the analog, mixed-signal, and mmWave design organization and own its silicon from architecture through volume production. You will set technical direction, lead and grow a team of senior designers, and be accountable for delivering silicon that meets performance, power, schedule, and yield targets. We are looking for a highly technical leader who has taken multiple products from concept to high-volume manufacturing and knows what it takes to design for first-pass success and production robustness.

## Key Responsibilities

- Build, lead, and mentor a high-performing team of analog, mixed-signal, RF/mmWave, and layout engineers; recruit top talent and foster a culture of technical rigor, ownership, and collaboration.
- Define the architecture and specifications for analog and mixed-signal IP, including high-speed ADCs and DACs, modulator drivers, transimpedance amplifiers and analog front ends, PLLs and clock generation/distribution, SerDes and high-speed I/O, voltage references, and on-chip regulators.
- Own silicon through the full lifecycle: specification, schematic and layout, verification, tape-out, silicon bring-up, characterization, qualification, and production release.
- Represent analog within the company. Negotiate specifications, schedules, and budgets the team can meet. Keep the team informed of company priorities and decisions, and report status, risks, and mitigation plans to the VP of VLSI.
- Guide the design of low-power precision analog blocks and high-speed mixed-signal circuits, driving aggressive energy-per-operation targets across the OPU system.
- Collaborate with the photonics team and oversee the development of millimeter-wave circuits and interfaces, including transceivers, LNAs, PAs, mixers, VCOs, and high-frequency passives, with a focus on EM modeling and package co-design.
- Maintain disciplined design data management. Establish and enforce robust design methodologies: PVT and Monte Carlo analysis, reliability (EM/IR, aging, ESD, latch-up), mismatch and noise budgeting, and rigorous design reviews at every milestone.
- Evaluate and adopt new tools, including AI-assisted design and verification.
- Drive design-for-manufacturability and design-for-test, working with test engineering to define strategy, trim and calibration schemes, and production test coverage.
- Lead silicon debug and root-cause analysis, and drive yield improvement and corner-lot correlation with foundry, OSAT, and product engineering partners.
- Partner closely with the photonics, digital, packaging, systems, and firmware teams to co-optimize the electro-optical interface and ensure system-level integration.

## Qualifications

- 15+ years of experience in analog, mixed-signal, and/or RF IC design, including 5+ years leading design teams at the manager or director level.
- Proven track record of bringing analog/mixed-signal products from concept through tape-out and validation into high-volume production, including qualification, yield ramp, and production test.
- Deep, hands-on expertise in low-power, high-precision analog and high-speed mixed-signal design, including data converters, PLLs, high-speed transceivers, and amplifiers.
- Demonstrated experience with millimeter-wave or high-frequency RF circuit design and the associated EM simulation, modeling, and measurement techniques.
- Strong working knowledge of advanced CMOS, FinFET, and/or SiGe BiCMOS process technologies and their implications for analog performance and reliability.
- Proficiency with industry-standard design and verification flows, including Cadence Virtuoso and Spectre and EM tools such as EMX.
- Experience working with foundries and OSATs, and a solid understanding of DFT, ATE test development, trimming and calibration, and failure analysis.
- Structured, organized approach to running a team and a design flow. Adaptable as tools, priorities, and the organization change.

## Preferred Skills

- PhD in Electrical Engineering, Computer Engineering, Physics, or related fields.
- Experience designing electronics for integrated photonics or optical interconnects, such as modulator drivers, TIAs, laser drivers, or co-packaged optics.
- Background in electronic-photonic co-design, including heterogeneous integration or 3D stacking of electronic and photonic dies.
- Experience with high-speed (e.g., 112G/224G PAM4 SerDes) wireline standards or mmWave wireless/radar products.
- Experience with ultra-low-power circuit techniques, including subthreshold design, dynamic power management, and energy-efficient data conversion.
- Familiarity with advanced packaging, signal and power integrity, and chip-package-board co-simulation.
- Experience building a team and supporting infrastructure in a startup setting.
- A record of patents, publications, or recognized contributions.

## What We Offer

This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.

## Benefits

Join a team that invests in your future and your well-being. At Neurophos, we offer:

- 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
- Unlimited PTO. No rigid vacation banks, just a focus on delivery.
- 401(k) matching and stock option opportunities to ensure our success is your success.
- Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
- Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

## About Neurophos

## Company Overview
- **One-liner**: Neurophos develops photonic AI chips (Optical Processing Units) that perform matrix multiplications at the speed of light, aiming to replace traditional GPUs in data-center inference workloads.
- **Entity Type**: Private, Series A
- **Headquarters**: Austin, Texas, USA (with an additional office in San Jose, California)
- **Founded**: 2020
- **Founders**: Patrick Bowen (CEO, Co-Founder) and Andrew Traverso (Chief Scientist, Co-Founder); other co-founders may include Preston Woo and Hod Finkelstein (CEO, CTO roles indicated on team page).

## Core Business
- **Primary industry**: Semiconductor / Photonic AI Hardware
- **Target customers**: B2B – hyperscale data centers, enterprise AI infrastructure providers
- **Mission/purpose**: “We’re building the first programmable light-speed computer” – solving energy and scalability challenges in AI data centers by using optical rather than electronic computation.

## Products & Services
- **Optical Processing Unit (OPU)**: A photonic AI chip that integrates over one million micron-scale optical processing components on a single die. It performs matrix multiplications in-memory at the speed of light, delivering up to 100x the energy efficiency of traditional GPUs and NVIDIA servers while fitting in a single-GPU form factor. The chip uses an active, programmable metasurface and silicon photonics to achieve 0.47 ExaOPS performance in a 1m x 1m footprint. First systems are targeted for early 2028, with production ramp in mid-2028.

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Total funding raised = **$119.2M** (including a $110M Series A closed in early 2026)
- **Notable Investors**: Gates Frontier (lead), M12 (Microsoft’s venture fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, MetaVC Partners, Gaingels, Mana Ventures, and 22+ others.
- **Growth Signals**: 
  - Recognized on EE Times Silicon 100 list for several consecutive years.
  - Over 300 patents filed and protected.
  - Rapid hiring after Series A – “hypergrowth phase” as per press release.
  - Team includes veterans from NVIDIA, AMD, Apple, Meta, Google, Magic Leap, Micron, Qualcomm, Samsung, and other photonic/AR companies.

## Competitive Advantages
- **Metasurface optical transistors** that are **10,000x smaller** than traditional photonic components, enabling unprecedented density – millions of weights fit in the area of a postage stamp.
- **300+ patents** covering optical metamaterials, neural network accelerators, and machine learning hardware.
- **Energy efficiency**: Up to 100x improvement over existing electronic solutions (e.g., GPUs), directly addressing the power constraints of hyperscale AI inference.
- **Size/performance**: OPU delivers the performance of a 3,000-pound server in the size and power envelope of a single GPU.

## Strategic Focus
- **Commercialization**: First customer evaluations begin in 2026; first OPU systems target early 2028 production ramp.
- **Talent acquisition**: Scaling the team aggressively across analog design, photonics, architecture, and software to meet “hypergrowth” demand.
- **Partnerships**: Leveraging investors like Bosch Ventures (industrial IoT), Aramco Ventures (energy), and M12 (cloud/AI) to align with large-scale data center customers.

## Why Work Here
- **Culture**: In-office, on‑site work culture in Austin, TX (primary) and San Jose, CA. Described as a “world-class team” with leaders from top semiconductor and tech companies.
- **Growth**: Joining at a hypergrowth scale‑up stage with significant funding and a clear path to production; opportunities to shape the architecture and engineering of a new computing paradigm.
- **Engineering focus**: 34 out of 40 total employees are in product + tech roles, indicating a highly technical, R&D-driven environment.
- **Impact**: Work on cutting-edge optical computing that could redefine AI hardware efficiency; involvement in everything from silicon photonics to compiler software.
- **Notable perks**: Not explicitly listed, but being a well-funded deep-tech startup likely offers competitive equity, technical challenges, and direct mentorship from industry veterans.

## Sources
1. [neurophos.com](https://www.neurophos.com/)
2. [neurophos.com/careers](https://www.neurophos.com/careers)
3. [neurophos.com/team](https://www.neurophos.com/team)
4. [cbinsights.com](https://www.cbinsights.com/company/neurophos)
5. [builtin.com](https://builtin.com/company/neurophos)

## Other roles at Neurophos

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- [Senior/Staff BEOL Process Integration Engineer](https://feeny.ai/job/senior-staff-beol-process-integration-engineer-neurophos-leuven-t70g32b8rjvj) — Leuven, Belgium
- [Chief Engineer, Prototype System Integration and Experimentation](https://feeny.ai/job/chief-engineer-prototype-system-integration-and-experimentation-neurophos-austin-25tqc715f1xs) — Austin, TX
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