---
title: 'DSP - FEC Design Engineer at Celero Communications, Inc.'
canonical: 'https://feeny.ai/job/dsp-fec-design-engineer-celero-communications-inc-ottawa-ontario-canada-and-v0ph40xnhxk5'
type: 'job'
last_seen: '2026-09-11'
---

# DSP - FEC Design Engineer at Celero Communications, Inc.

- **Company:** Celero Communications, Inc.
- **Location:** Ottawa Ontario Canada and Vancouver British Columbia, Canada
- **Posted:** 2026-03-17
- **Last confirmed live:** 2026-09-11
- **Apply:** https://job-boards.greenhouse.io/celerocommunicationsinc/jobs/4181252009

## Job description

About the Role:

Celero Communications Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure.

We are looking for skilled and motivated engineers to join our team and help us build optical transceivers for next-generation optical modems. The ideal candidate must have a strong theoretical background in coding theory, digital communications, and error correction techniques, with experience developing high-performance forward error correction (FEC) algorithms for high-speed communication systems. Candidates with industry experience are preferred.

Locations: Ottawa, Ontario, Canada and Vancouver, British Columbia, Canada

## Key Responsibilities

- Research, develop, and evaluate forward error correction (FEC) schemes for high-speed optical communication systems.
- Design and optimize soft-decision FEC algorithms suitable for high-throughput optical modem implementations.
- Develop and evaluate coding schemes such as LDPC, staircase codes, or related high-performance FEC architectures.
- Model and simulate FEC performance in optical communication systems, including interaction with DSP blocks and channel impairments.
- Analyze performance trade-offs including coding gain, latency, throughput, and implementation complexity.
- Develop floating-point and fixed-point simulation models for algorithm verification.
- Implement bit-accurate and cycle-accurate models supporting ASIC implementation.
- Collaborate closely with DSP, ASIC, firmware, and verification teams to ensure efficient hardware implementation.
- Document algorithm design and simulation results.

## Preferred Qualifications

- Master’s or Ph.D. degree in Electrical Engineering, Mathematics, Computer Engineering, or related field.
- Strong background in coding theory and error correction algorithms.
- Experience with FEC schemes for communication systems, particularly soft-decision FEC.
- Familiarity with LDPC, staircase codes, product codes, or related modern FEC techniques.
- Experience evaluating coding gain, BER performance, and decoder complexity.
- Programming experience in C/C++, Python, MATLAB, or similar languages.
- Experience in modeling communication systems.
- Familiarity with DSP algorithms for communication systems.
- Experience with version control systems, specifically GitHub.
- Familiarity with hardware implementation considerations and languages such as Verilog or VHDL is a plus.
- Team player with a mindset focused on the successful delivery of the first product.

## Why Join Us

- The chance to play a foundational role at a high-growth semiconductor start-up.
- Work on cutting-edge optical communication technologies powering AI and hyperscale data centers.
- A collaborative, international team culture where ideas and initiative are valued.
- The opportunity to grow alongside Celero as we scale and shape the future of our industry.

Salary Range

$150,000 - $250,000 Base Annually The final offer will be determined based on job-related skills, experience, qualifications, and location.

## About Celero Communications, Inc.

## Company Overview
- **One-liner**: Celero Communications develops advanced coherent DSP solutions that enable high-bandwidth, low-power optical connectivity for AI infrastructure, eliminating distance bottlenecks in data centers.
- **Entity Type**: Private (Series B; total funding $148.4M per LinkedIn, $140M per company press release)
- **Headquarters**: Irvine, California, USA
- **Founded**: 2024
- **Founders**: Nariman Yousefi (CEO, President & Co-founder) and Oscar Agazzi (CTO & Co-founder)

## Core Business
- **Primary industry**: Semiconductor manufacturing / optical networking for AI infrastructure
- **Target customers**: B2B – hyperscale data centers, AI cloud providers, and large-scale accelerated computing clusters
- **Mission**: “Deliver the optical performance and scalability needed for the next generation of accelerated computing” [celero.inc](https://celero.inc/about/)

## Products & Services
- **Coherent DSP Platform**: A digital signal processor that provides light-speed performance, bandwidth efficiency, and scalable optical links for AI accelerators, servers, and clusters. The technology is described as 100x more efficient than conventional optical transmission and is designed for interoperability across diverse AI and cloud platforms. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/)

## Market Standing
- **Valuation**: Not publicly disclosed
- **Key Metric**: Total funding of **$148.4 million** (Seed $8.4M led by Sutter Hill Ventures; Venture Round $40M; Series B $100M led by CapitalG) [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Notable Investors/Partners**: Sutter Hill Ventures (lead seed & Series A), CapitalG (lead Series B), plus other undisclosed investors in venture round [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Growth Signals**: Founded in 2024, already employs **93 people** with a monthly headcount growth of **+9.3%**. Operates design centers in Irvine (CA), Ottawa (Canada), and Córdoba (Argentina). [linkedin.com](https://www.linkedin.com/company/celero-communications)

## Competitive Advantages
- **Founding team** consists of industry pioneers from Marvell, Inphi, Broadcom, and ClariPhy with decades of experience in analog design, digital signal processing, and optical networking. [celero.inc](https://celero.inc/about/)
- **Coherent DSP technology** that eliminates distance bottlenecks, delivering 100x more efficient optical transmission for scale-across AI infrastructure. [celero.inc](https://celero.inc/)
- **System flexibility and interoperability** across diverse AI and cloud platforms, making it easier for data centers to adopt. [celero.inc](https://celero.inc/)

## Strategic Focus
- **Current priorities**: Scaling AI infrastructure connectivity by delivering high-bandwidth, low-power optical links; expanding engineering teams across all design centers; and building energy-efficient systems that redefine how data centers connect. [celero.inc](https://celero.inc/careers/)

## Why Work Here
- **Culture**: Described as driven by curiosity, precision, and the challenge of making AI systems faster and more energy-efficient. Employees collaborate with global experts in coherent DSP and optical engineering. [celero.inc](https://celero.inc/careers/)
- **Work model**: On-site/hybrid at three locations – Irvine, CA (HQ); Ottawa, Canada; and Córdoba, Argentina. Multiple engineering roles (Analog Design, ASIC, DSP, Firmware, Verification) are posted with specific location requirements. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc)
- **Notable perks**: Opportunity to work on next-generation AI infrastructure technology alongside industry pioneers. The company emphasizes building scalable, energy-efficient systems and offers roles across R&D, operations, and manufacturing. [celero.inc](https://celero.inc/careers/)

## Sources
1. [celero.inc](https://celero.inc/) – Company homepage and product description
2. [celero.inc](https://celero.inc/about/) – About page (founding, leadership, mission)
3. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/) – Press release on $140M funding
4. [linkedin.com](https://www.linkedin.com/company/celero-communications) – LinkedIn company page (funding details, headcount, locations, employee breakdown)
5. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc) – Careers page (open positions, locations)

## Other roles at Celero Communications, Inc.

- [High-Speed Analog Layout Design Engineer](https://feeny.ai/job/high-speed-analog-layout-design-engineer-celero-communications-inc-cordoba-66dn2b6kaepy) — Córdoba, Argentina
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-jjzw8wst9kw4) — Ottawa, Canada
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-xb3kfd5e3s5y) — San Jose, CA
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-vahmmaqvrh01) — Irvine, CA
- [IT Help Desk](https://feeny.ai/job/it-help-desk-celero-communications-inc-cordoba-a16t8nfqdwcf) — Córdoba, Argentina
- [ASIC Design Engineer – DSP / Analog / SerDes](https://feeny.ai/job/asic-design-engineer-dsp-analog-serdes-celero-communications-inc-ottawa-pd4fx2w60yhv) — Ottawa, Canada
- [ASIC Design Engineer – DSP / Analog / SerDes](https://feeny.ai/job/asic-design-engineer-dsp-analog-serdes-celero-communications-inc-irvine-we9e7z3fvx1m) — Irvine, CA
- [Principal Product Engineer](https://feeny.ai/job/principal-product-engineer-celero-communications-inc-singapore-derwypn4kenf) — Singapore
- [Principal Analog Design Engineer](https://feeny.ai/job/principal-analog-design-engineer-celero-communications-inc-vancouver-british-sz02fec2vbsc) — Vancouver British Columbia, Canada
- [Principal Analog Design Engineer](https://feeny.ai/job/principal-analog-design-engineer-celero-communications-inc-ottawa-eqcyjq44gc71) — Ottawa, Canada