---
title: 'Edge AI SDK Lead at Velaura'
canonical: 'https://feeny.ai/job/edge-ai-sdk-lead-velaura-santa-clara-fg28np6v11fb'
type: 'job'
last_seen: '2026-10-16'
---

# Edge AI SDK Lead at Velaura

- **Company:** Velaura
- **Location:** Santa Clara, CA
- **Compensation:** $200k–$300k
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-10-01
- **Last confirmed live:** 2026-10-16
- **Apply:** https://jobs.lever.co/velaura/0c7d0575-db1e-4733-bcbd-d96b3fa3e4be

## Job description

## Role Overview

We are looking for an Edge AI SDK Lead to own the customer-facing software experience for Velaura’s AI SoC. This role will define and lead development of public APIs, SDK structure, command-line tools, sample applications, documentation, developer workflows, model and camera examples, developer portal content, compatibility matrices, and the path from “unboxing the eval kit” to running real robotics and AI workloads. This is an on-device role: the SDK runs on our silicon, not in the cloud.

## Responsibilities

- Own SDK architecture, public APIs, command-line tools, sample applications, documentation strategy, and developer workflows.

- Set the API standards, versioning, error handling, logging, packaging, compatibility, and deprecation policies across platform, AI runtime, camera, and robotics components.

- Lead the developer experience for installing the SDK, flashing boards, running demos, deploying models, using cameras, and integrating with applications.

- Work with AI, multimedia, robotics, and model-zoo teams to deliver model examples, camera-to-NPU pipelines, ROS examples, containers, and reference applications.

- Own developer documentation structure, getting-started guides, tutorials, API references, troubleshooting guides, migration guides, and known-issues workflows.

- Partner with Tools/Release on downloads, package repos, release notes, compatibility matrices, SDK artifacts, archived releases, checksums, and versioned documentation.

- Help define developer portal requirements including docs, downloads, model/app catalog, camera compatibility, KB integration, entitlement/access control, and support-bundle workflows.

- Ensure SDK quality by partnering with SQA on examples, docs validation, install tests, compatibility tests, and release readiness.

- Represent the customer developer perspective in architecture and prioritization discussions.

- Hire, mentor, and lead engineers focused on SDK APIs, developer tools, documentation systems, developer portal integration, and sample applications.

Required Qualifications

- Strong experience building and shipping SDKs, APIs, or developer tools for embedded or edge hardware (e.g., SoCs, AI accelerators, dev kits, camera or robotics platforms) - software that customers install and run on the device itself. Experience limited to cloud, web, or backend SDKs/APIs does not meet this requirement.

- Strong C/C++ for embedded targets and Python experience, with ability to design clean APIs and production-quality examples.

- Hands-on experience developing for embedded Linux targets, such as cross-compilation and toolchains, BSPs, board bring-up and flashing, device drivers, or on-device packaging and deployment.

- Strong sense of developer experience, documentation quality, API usability, and release discipline.

- Ability to work across kernel, runtime, compiler, multimedia, robotics, tools, SQA, and product teams.

- Experience translating complex low-level capabilities into usable customer-facing software.

- Experience leading technical teams or major SDK/API architecture areas.

## Preferred Qualifications

- Experience with AI accelerator SDKs, robotics SDKs, Jetson-like platforms, edge AI products, or semiconductor developer kits.

- Familiarity with ONNX/PyTorch/TFLite model flows, ROS 2, GStreamer, OpenCV, containers, Linux packaging, or Python packaging.

- Experience building developer portals, documentation sites, SDK installers, CLI tools, sample catalogs, knowledge bases, or model zoos.

- Experience with API governance, semantic versioning, compatibility matrices, customer migration guides, and release notes.

- Experience working with early customers, field teams, support teams, or developer relations.

- Ability to write excellent technical documentation and set a high bar for customer-facing materials.

Why Velaura? Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world. This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

## Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans. Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: careers@velaura.ai. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

## About Velaura

## Company Overview
- **One-liner**: Velaura (formerly Auradine) is a semiconductor and systems company building ultra-low-power compute infrastructure for AI workloads across cloud, edge, and physical AI applications.
- **Entity Type**: Private (Series C, $314M total funding)
- **Headquarters**: Santa Clara, California, USA
- **Founded**: 2023 (as Auradine; rebranded to Velaura AI in 2026)
- **Founders**: Co-founded by Rajiv Khemani (CEO), YJ Kim (President, Products), Sanjay Gupta (President, Strategy & GTM), and Manu Gulati (Chief Development Officer)

## Core Business
- **Primary Industry**: Semiconductor design, AI compute infrastructure, ultra-low-power ASICs
- **Target Customers**: Hyperscale data centers, AI/ML platform providers, edge computing companies, and physical AI (robotics, automotive) OEMs — primarily **B2B Enterprise**
- **Mission**: To deliver proven, breakthrough, ultra-low-power compute for cloud, edge, and physical AI applications, solving the power bottleneck that constrains AI scaling.

## Products & Services
- **Proprietary Ultra-Low-Power Digital Design Technology**: Patented IP and toolflow that reduces power consumption of arithmetic operations by 2–4x on leading process nodes, translating to ~$650–$1,300/chip in power savings over 3 years. Output is optimized GDS or chiplets.
- **Custom AI Accelerators (ASICs)**: Full-custom silicon solutions for AI inference and training workloads, co-designed with customers (RTL input → optimized GDS).
- **Engagement Model**: Customer provides RTL design and priorities; Velaura applies its proprietary methodology, low-voltage libraries, and custom circuit expertise to deliver power-optimized chip designs with proven yield and reliability.

## Market Standing
- **Valuation/Market Cap**: Not publicly disclosed (private company)
- **Key Metric**: **$314M total funding** across 4 rounds
  - Series A (2023): $71M from 6 investors
  - Debt Financing (2023): $10M
  - Series B (2024): $80M from 7 investors
  - Series C (2025): $153M from 8 investors
- **Notable Investors/Partners**: Backed by top-tier VCs (specific names not publicly listed; investors include firms with deep semiconductor expertise) — talent sources include Qualcomm, Arm, Apple, Google, NVIDIA, Intel, Palo Alto Networks, Stripe
- **Growth Signals**:
  - Rebranded from Auradine to Velaura AI in August 2026, signaling strategic expansion into AI compute
  - Added Manu Gulati (ex-NUVIA co-founder, Apple/Google silicon architect) as Co-founder & Chief Development Officer
  - Added Aditya Grover (Co-founder & CTO of Inception, Stanford PhD, part of the team that invented Diffusion models) as Founding Advisor
  - Workforce of 42 employees growing at +4.3% monthly; headcount split ~47% US / 39% India
  - Offices in Santa Clara, CA (HQ) and additional US location, with hiring across hardware and software engineering in Bangalore, Austin, and Boston

## Competitive Advantages
- **Patented ultra-low-power digital design technology** field-proven over multiple years across tens of millions of ASICs deployed with world-class yield and reliability
- **Founding team with exceptional pedigree**: seasoned entrepreneurs and technologists from Qualcomm, Marvell, NVIDIA, Intel, Palo Alto Networks, Apple, Google, and NUVIA (acquired by Qualcomm for ~$1.5B)
- **Systems-level thinking**: combines deep silicon expertise with AI/ML domain knowledge to tackle power as the primary bottleneck for AI at scale
- **Engagement model** that allows customers to leverage Velaura’s IP without fully outsourcing chip design — outputs optimized GDS or chiplets on latest process nodes

## Strategic Focus
- **Scale ultra-low-power compute across three domains**: cloud data centers, edge/enterprise, and physical AI (robotics, autonomous systems)
- **Hire aggressively** for engineering leadership: compiler development, platform software, CAD/methodology, RTL, design verification, advanced packaging, AI architecture, and hardware/software co-design
- **Productize its proprietary IP** into standard offerings for hyperscalers and AI chip companies
- **Continue raising capital** (largest round was $153M Series C in April 2025) to fund expansion

## Why Work Here
- **Culture**: Deep engineering DNA and systems-level thinking — the team is solving one of AI’s hardest physical constraints (power) with proven silicon technology
- **Growth trajectory**: Rapidly scaling startup (42 employees, +4.3% monthly headcount growth, $314M raised) with a clear path to becoming a key infrastructure provider for the AI era
- **Leadership**: Led by industry veterans (NUVIA, Apple, Google, Qualcomm) who have built billion-dollar silicon companies and products powering billions of devices
- **Work environment**: On-site roles in Santa Clara, CA; Austin, Texas; and Bangalore, India. Remote/hybrid policy not specified but multiple office locations suggest flexible collaboration.
- **Impact**: Opportunity to work on cutting-edge AI hardware design, from architecture through tape-out and deployment, with direct impact on the power efficiency of the world’s largest AI clusters
- **Notable perks**: Not publicly detailed, but the company’s focus on high-end engineering talent suggests competitive compensation, equity, and exposure to top-tier semiconductor and AI technology

## Sources
1. [velaura.ai](https://velaura.ai/introducing-velaura-ai/)
2. [velaura.ai](https://velaura.ai/team/)
3. [velaura.ai](https://velaura.ai/low-power-ai-compute/)
4. [jobs.lever.co/velaura](https://jobs.lever.co/velaura/)
5. [linkedin.com](https://linkedin.com/company/velaura-ai-inc)
6. [wellfound.com](https://wellfound.com/company/velaura-ai) (Apollo data extracted on financials and headcount)

SUGGESTED_INDUSTRY: semiconductor-manufacturing-robotics-ai-infrastructure
_(Note: The above slug is not in the provided list. Closest match from the list is `artificial-intelligence`. However, given the company's core business is semiconductor design and power-efficient AI compute infrastructure, `manufacturing-robotics` or `infrastructure` also fit. For strict adherence to the provided list: `artificial-intelligence` is the best single choice.)_

## Other roles at Velaura

- [RTL Engineer Memory Subsystem](https://feeny.ai/job/rtl-engineer-memory-subsystem-velaura-santa-clara-jtrax095faxj) — Santa Clara, CA
- [CAD Back-end Lead](https://feeny.ai/job/cad-back-end-lead-velaura-bengaluru-f130hrc0va9c) — Bengaluru, India
- [SoC Design Verification Lead](https://feeny.ai/job/soc-design-verification-lead-velaura-santa-clara-5ffrthtymcq8) — Santa Clara, CA
- [SoC Design Verification Engineer](https://feeny.ai/job/soc-design-verification-engineer-velaura-santa-clara-4re9r1jbzc50) — Santa Clara, CA
- [Office Admin / Receptionist](https://feeny.ai/job/office-admin-receptionist-velaura-santa-clara-asc5tq6ff9ze) — Santa Clara, CA
- [Sr Engineer CAD Pre-Silicon Front End](https://feeny.ai/job/sr-engineer-cad-pre-silicon-front-end-velaura-santa-clara-91g66vhzqqt3) — Santa Clara, CA
- [Director of IT Infrastructure & Operations](https://feeny.ai/job/director-of-it-infrastructure-operations-velaura-santa-clara-46t1yb690v9g) — Santa Clara, CA
- [RTL Power Engineer](https://feeny.ai/job/rtl-power-engineer-velaura-santa-clara-jyj4n03rckrf) — Santa Clara, CA
- [Design Verification Engineer- AI Accelerator](https://feeny.ai/job/design-verification-engineer-ai-accelerator-velaura-santa-clara-15tk23smaz5x) — Santa Clara, CA
- [Design Verification Engineer- CPU](https://feeny.ai/job/design-verification-engineer-cpu-velaura-santa-clara-d1bkx2h2dj9g) — Santa Clara, CA