--- title: 'Formal Verification - DV at Etched' canonical: 'https://feeny.ai/job/formal-verification-dv-etched-san-jose-ej833spab33r' type: 'job' last_seen: '2026-10-12' --- # Formal Verification - DV at Etched - **Company:** [Etched](https://feeny.ai/companies/etched) - **Location:** San Jose, CA - **Employment:** full-time - **Work type:** onsite - **Posted:** 2026-06-10 - **Last confirmed live:** 2026-10-12 - **Apply:** https://jobs.ashbyhq.com/etched/07b00790-2817-4863-a330-b0caf2322460/application **Skills:** SystemVerilog, SystemVerilog Assertions, Formal Verification, Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, RTL, UVM, Digital Design, Computer Architecture, SoC Interfaces, Python, TCL, Perl, Systolic Arrays, DMA Engines, NoCs, Memory Subsystems, PCIe, Ethernet > We are seeking a Senior Formal Verification Engineer to drive formal verification across custom IP, interface IP, and SoC subsystems. You will define verification strategies, build formal environments, and debug complex RTL to prove design correctness and improve verification closure. ## Job description ## About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are seeking a Formal Verification Engineer to join our ASIC Design Verification team. You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU subsystems, low-power peripherals, and vendor IP wrappers. You will work closely with architects, RTL designers, DV engineers, emulation teams, and software/firmware teams to prove design correctness, expose deep corner-case bugs, and improve verification closure across the full chip. ## Key Responsibilities - Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic. - Develop formal verification plans covering functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom. - Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models. - Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics to establish formal sign-off confidence. - Work with architects and RTL designers to translate design intent and specifications into high-value formal properties and closure criteria. - Partner with UVM DV, emulation, software, and firmware teams to align formal verification with simulation, coverage, regressions, and bring-up. - Debug complex RTL, protocol, datapath, connectivity, and integration bugs using formal counterexamples, waveforms, and design analysis. - Contribute to formal sign-off methodology, regression automation, reporting, and design-for-formal best practices. You May Be a Good Fit If You Have - 5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon. - Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology. - Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal. - Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces. - Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models. - Strong debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports. - Experience collaborating across architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams. - You thrive in a fast-paced startup environment and can take ownership of ambiguous, high-impact verification problems. Strong Candidates May Also Have Experience With - Formal verification of systolic arrays, DMA engines, NoCs, memory subsystems, arithmetic datapaths, PCIe, Ethernet, AXI/AMBA, CPU interfaces, or low-power controllers. - Protocol compliance checking, connectivity checking, register verification, datapath validation, reset verification, or deadlock/livelock analysis. - Vendor IP integration, encrypted or black-box IP verification, VIP configuration, and contract-based verification around subsystem boundaries. - Sequential LEC, floating-point or integer arithmetic proofs, cache coherency checks, interrupt handling, or memory-mapped IO verification. - Scripting in Python, TCL, Perl, or similar for automation, regression management, debug, and dashboarding. - ## Benefits - Medical, dental, and vision packages with generous premium coverage - $500 per month credit for waiving medical benefits - Housing subsidy of $2.5k per month for those living within walking distance of the office - Relocation support for those moving to San Jose (Santana Row) - Various wellness benefits covering fitness, mental health, and more - Daily lunch + dinner in our office ## How we’re different Etched believes in the [Bitter Lesson](http://www.incompleteideas.net/IncIdeas/BitterLesson.html). We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed. ## About Etched ## Company Overview - **One-liner**: Etched designs and manufactures specialized ASICs (application-specific integrated circuits) that are hardwired to run transformer-based AI models, offering an order-of-magnitude improvement in inference cost and energy efficiency over general-purpose GPUs. - **Entity Type**: Private (Series B / later stage; total raised $800M as of June 2026) - **Headquarters**: San Jose, California, USA (also has offices in Cupertino, CA; Sacramento, CA; and small presence in Taiwan, Canada, UK, Bulgaria) - **Founded**: 2022 - **Founders**: Gavin Uberti (CEO), Robert Wachen (President & COO), Chris Zhu (Co-Founder) ## Core Business - **Primary industry**: AI hardware / semiconductor design / computer hardware manufacturing - **Target customers**: Frontier AI labs, hyperscalers, and enterprises running large-scale transformer inference workloads (B2B, enterprise) - **Mission / purpose**: Build hardware for superintelligence – specifically, the world’s most powerful servers for transformer inference. ## Products & Services - **Sohu Chip (ASIC)**: A transformer-specific ASIC manufactured by TSMC. It burns the transformer architecture directly into silicon, eliminating the overhead of general-purpose GPUs for inference. - **Frontier Inference Clusters**: Full-stack systems that bundle the Sohu chip with custom-designed racks, networking, and software. Customers place orders for complete systems, not just chips. Etched claims they deliver more tokens per dollar and per watt for dense models, sparse MoEs, diffusion models, and more. - **Software Stack**: Includes compiler and runtime optimizations built by a team with deep experience (former Apache TVM developer, ex-Google TPU software lead). ## Market Standing - **Valuation**: $5 billion post-money valuation (as of December 2025 / disclosed June 2026) - **Key Metric**: $1 billion in contract orders (booked) for its systems; total funding of $800M (including an unannounced $500M round closed Dec 2025 led by Stripes) - **Notable Investors**: Stripes (lead), VentureTech Alliance, Jane Street, Hudson River Trading, Two Sigma, Ribbit Capital. Angel investors include Andrej Karpathy, Geoffrey Hinton, Fei-Fei Li, Arthur Mensch, Scott Wu, Stanley Druckenmiller, Peter Thiel. Earlier backers: Positive Sum, Primary Venture Partners. - **Growth Signals**: - Headcount: 258 employees (as of mid-2026), up 141% year-over-year - 100+ active job postings across engineering, operations, and business functions - $500M raise in late 2025; first chip manufactured by TSMC in 2025 and now being tested with customers - Talent sources include Google (21), Apple (17), NVIDIA (16), Tesla (11), Intel (10), AMD (5) ## Competitive Advantages - **Transformer-specific architecture**: Unlike GPUs (which are general-purpose), Etched’s chip is hardwired only for transformer operations, enabling drastically lower cost and latency for today’s dominant AI model architecture. - **Full-stack system play**: By selling entire inference clusters (chip + rack + software), Etched captures more value and delivers a turnkey solution competitive with NVIDIA’s DGX/HGX systems. - **Deeply experienced leadership**: - CEO Gavin Uberti (Harvard math researcher, AI compiler expert, Apache TVM contributor) - President Robert Wachen (co-founded Prod AI incubator; Thiel Fellow) - VP of Platform (ex-NVIDIA 22 years, built HGX/DGX systems) - VP of Software (ex-Google DeepMind, lead TPU v1–v5 software) - Chief Architect Saptadeep Pal (former Auradine co-founder, chiplet expert) - VP of Hardware Engineering Ajat Hukkoo (ex-Cypress CTO, shipped >$1B revenue products) ## Strategic Focus - **Scale manufacturing and customer deliveries**: With the first chip successfully fabricated, the company is now testing production systems and aims to fulfill $1B in pre-orders. - **Expand engineering talent**: Aggressively hiring across silicon design, validation, infrastructure, optics, and software to support volume ramp. - **Maintain technological lead**: Continue refining the ASIC for future transformer variants and MoE mixtures while building out a partner ecosystem. ## Why Work Here - **Mission-driven, high-impact engineering**: “Building the hardware for superintelligence” – the company is solving one of the hardest problems in compute (inference efficiency) with a focused team. - **Top-tier team and learning environment**: Colleagues from Google, NVIDIA, Apple, Tesla, Broadcom, and Intel; exposure to full-stack chip-to-system design. - **In-office culture**: All roles are in-office (Cupertino and San Jose, CA). The company emphasizes on-site collaboration for hardware development. Notable perks are not heavily advertised, but compensation is competitive for the AI hardware space (equity-heavy). - **Growth trajectory**: 141% headcount growth YoY, hundreds of open roles, and a $5B valuation signal strong backing and career acceleration potential. - **Intellectual challenge**: Work on chip simulation, RTL design, system validation, or software infrastructure for cutting-edge AI inference. ## Sources 1. [etched.com/careers](https://www.etched.com/careers) 2. [builtin.com/company/etched](https://builtin.com/company/etched) 3. [linkedin.com/company/etched-ai](https://www.linkedin.com/company/etched-ai) 4. [cbinsights.com/company/etched](https://www.cbinsights.com/company/etched) 5. [techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/](https://techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/) ## Other roles at Etched - [General Ledger Accountant, Payroll](https://feeny.ai/job/general-ledger-accountant-payroll-etched-san-jose-xr9dcmpj9szw) — San Jose, CA - [SMT Process Engineer (Greenfield Factory)](https://feeny.ai/job/smt-process-engineer-greenfield-factory-etched-san-jose-kkv9pgb90n7e) — San Jose, CA - [SMT Line Lead](https://feeny.ai/job/smt-line-lead-etched-san-jose-r3q7mdgetr2w) — San Jose, CA - [Capital Projects - Electrical Infrastructure Engineer](https://feeny.ai/job/capital-projects-electrical-infrastructure-engineer-etched-san-jose-8s9m4qf7ck70) — San Jose, CA - [Inventory Manager](https://feeny.ai/job/inventory-manager-etched-taipei-gca9fe0dct6r) — Taipei, Taiwan - [Applied Engineer, Hardware](https://feeny.ai/job/applied-engineer-hardware-etched-san-jose-vycr5g1nqq2v) — San Jose, CA - [Fleet Software Lead](https://feeny.ai/job/fleet-software-lead-etched-san-jose-svcqdg44dg89) — San Jose, CA - [Node Systems Lead](https://feeny.ai/job/node-systems-lead-etched-san-jose-cxzwasw32y5m) — San Jose, CA - [Head of Legal / General Counsel](https://feeny.ai/job/head-of-legal-general-counsel-etched-san-jose-npxz5yr6nfa0) — San Jose, CA - [MTS, Agent Research](https://feeny.ai/job/mts-agent-research-etched-san-jose-z6qrr0cehkyy) — San Jose, CA