---
title: 'Hardware Engineer, Design Verification at Normal Computing Corporation'
canonical: 'https://feeny.ai/job/hardware-engineer-design-verification-normal-computing-corporation-new-york-acjv43js3tha'
type: 'job'
last_seen: '2026-11-05'
---

# Hardware Engineer, Design Verification at Normal Computing Corporation

- **Company:** Normal Computing Corporation
- **Location:** New York, NY
- **Employment:** full-time
- **Work type:** hybrid
- **Posted:** 2026-07-15
- **Last confirmed live:** 2026-11-05
- **Apply:** https://jobs.ashbyhq.com/normalcomputing/d6d2797c-0201-4d7c-98cd-0317649dc78b

## Job description

Normal Computing | Build with Us Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London.

## The Role

Hybrid: 3 days a week in the office, in Mountain View, New York or London. As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs from architecture through tapeout, and help set the bar for the AI-assisted verification flows we are building for ourselves. You will own verification of complex IPs and subsystems, develop reusable verification infrastructure, and establish methodologies that enable efficient, scalable verification across our silicon programs. You will also work closely with our architecture, RTL, and software teams to integrate AI-assisted tools into everyday verification workflows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat.

## What You Will Own

- ASIC Design Verification: Own end-to-end verification of Normal's internal ASICs, including verification planning, testbench development, assertions, functional coverage, regression, and coverage closure through tapeout.
- Verification Architecture & Methodology: Develop scalable SystemVerilog/UVM verification environments, reusable VIP, scoreboards, reference models, and verification methodologies across IP, subsystem, and SoC levels.
- AI-Native Verification Workflows: Develop and integrate AI-assisted verification workflows, including specification analysis, test planning, testbench generation, debugging, and coverage closure. Review AI-generated verification collateral and help define what good looks like, so the tools the team builds raise the bar rather than lower it.
- Verification Infrastructure & Tooling: Build and maintain regression infrastructure, CI/CD integration, coverage analysis, and EDA tool flows to support efficient and repeatable ASIC verification.
- Cross-Functional Collaboration: Work closely with architecture, RTL design, physical design, and software teams to identify verification requirements, resolve design ambiguities, and drive silicon quality.

What Makes You a Great Fit

- 5+ years of experience in digital design verification for complex ASICs, SoCs, or IPs
- Advanced proficiency in SystemVerilog, UVM, SystemVerilog Assertions (SVA), and constrained-random verification
- Proven experience in end-to-end verification, including verification planning, testbench architecture, stimulus generation, scoreboards, and functional coverage closure
- Strong understanding of industry-standard protocols such as AXI, APB, AHB, or other SoC interconnects
- Experience with EDA simulation, debugging, and coverage tools such as Cadence Xcelium, SimVision, vManager, Synopsys VCS, or Verdi
- Strong scripting and automation skills using Python, Tcl, or similar languages
- Experience developing reusable verification environments and debugging complex RTL and system-level issues
- Strong communication and collaboration skills, with the ability to work across hardware and software teams

Bonus Points

- Experience building verification infrastructure and methodologies from the ground up for a new ASIC program
- Hands-on experience using LLMs, AI coding assistants, or agentic tools for RTL design and verification
- Experience with formal verification, power-aware verification, or emulation
- Exposure to AI accelerators, memory subsystems, in-memory computing, or unconventional compute architectures

## Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our [Applicant Privacy Notice](https://normalcomputing.com/applicant-privacy-notice).

## About Normal Computing Corporation

## Company Overview
- **One-liner**: Normal Computing builds AI-accelerated EDA software and physics-based ASICs to enable ultra-efficient hardware for the AI era.
- **Entity Type**: Private (Series B; total funding $92.5M)
- **Headquarters**: New York, New York, USA
- **Founded**: 2022
- **Founders**: Faris Sbahi (CEO), Matthias Tan (Co-Founder), and team of former Google Brain/Google X engineers and scientists

## Core Business
- Primary industry: Semiconductor design (EDA) and custom silicon (ASICs), powered by AI and probabilistic computing.
- Target customers: Large semiconductor design and manufacturing institutions (B2B, enterprise).
- Mission: "Rewriting AI foundations to advance the frontier of reasoning and reliability in the physical world" and enabling a virtuous cycle of self-improving AI hardware.

## Products & Services
- **[Normal EDA](https://normalcomputing.com/)**: An AI-driven electronic design automation platform that understands design intent from specification documents, generates hierarchical test plans with traceability, creates SystemVerilog stimulus, runs simulations, and tracks coverage. It continuously learns from team feedback to accelerate verification for complex chip designs.
- **[Normal ASICs](https://normalcomputing.com/)**: Physics-based custom ASICs that relax traditional computing assumptions (stochastic, stateful, asynchronous) to unlock orders-of-magnitude more efficient compute. Designed to converge hardware with the physical dynamics of AI models.

## Market Standing
- **Valuation/Market Cap**: Not publicly disclosed.
- **Key Metric**: **Total Funding** – $92.5M across multiple rounds (Seed, Venture, Grant, Series B). Notable recent round: $50M led by **Samsung Catalyst** in March 2026 [normalcomputing.com](https://normalcomputing.com/).
- **Notable Investors**: Samsung Catalyst Fund, Intel Ignite, First Spark Ventures, Celesta Capital, ARIA. Also partners with Fraunhofer IESE (DRAMBench benchmark).
- **Growth Signals**: Headcount grew **196.3% YoY** to 54 employees; operates across 6 countries (US, UK, Denmark, Switzerland, India, Canada); actively building open-source tools (e.g., a Verilog simulator built with AI: 580K lines in 43 days).

## Competitive Advantages
- **Physics-First Approach**: Unlike traditional digital logic, Normal’s ASICs embrace stochastic, stateful, and asynchronous computing – aligning hardware with the physics of AI models for dramatic efficiency gains.
- **Full-Stack Co-Design**: The combination of AI-native EDA tools and custom silicon creates a closed loop where software and hardware are co-optimized, shortening time-to-market and enabling workload-specific ASICs.
- **Deep AI Heritage**: Founders and team hail from Google Brain and Google X, bringing deep expertise in probabilistic ML, quantum AI, and physical-world reasoning.

## Strategic Focus
- **Scaling EDA Adoption**: Expanding Normal EDA’s use among top semiconductor companies to "make chip design look more like software".
- **AI Hardware Energy Crisis**: Tackling soaring power demands of AI by delivering ultra-efficient ASICs that can be produced for every workload.
- **Open-Source & Research**: Building community trust through open benchmarks (DRAMBench) and tools (CIRCT-based verification), while advancing formal methods and AI-driven simulation.

## Why Work Here
- **Hybrid Workspace**: Flexible in-office collaboration at offices in **New York (Flatiron HQ)**, **San Francisco**, **London**, and **Copenhagen**. In-person collaboration is valued but with flexibility; free lunch, snacks, and beverages in office.
- **Lean, High-Impact Team**: Small team (54 employees) where every member drives significant impact, works directly with customers, and owns meaningful parts of the product.
- **Interdisciplinary Challenges**: Work spans AI, probabilistic software, hardware, physics, and full-stack engineering – ideal for curious, passionate problem-solvers.
- **Strong Growth Trajectory**: Rapid headcount growth (+196% YoY), recent $50M Series B, and partnerships with industry giants signal a well-funded, high-potential startup.

## Sources
1. [normalcomputing.com](https://normalcomputing.com/)
2. [normalcomputing.com/about](https://normalcomputing.com/about)
3. [linkedin.com/company/normal-computing-corporation](https://www.linkedin.com/company/normal-computing-corporation)
4. [builtin.com/company/normal-computing](https://builtin.com/company/normal-computing)
5. [jobs.ashbyhq.com/normalcomputing](https://jobs.ashbyhq.com/normalcomputing)

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