---
title: 'Hardware Engineer, DFT at Normal Computing Corporation'
canonical: 'https://feeny.ai/job/hardware-engineer-dft-normal-computing-corporation-mountain-view-xv7mzqfbedsx'
type: 'job'
last_seen: '2026-10-29'
---

# Hardware Engineer, DFT at Normal Computing Corporation

- **Company:** Normal Computing Corporation
- **Location:** Mountain View, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-10-22
- **Last confirmed live:** 2026-10-29
- **Apply:** https://jobs.ashbyhq.com/normalcomputing/41b9c0fe-5483-4dba-a1a8-517d88c9a9ae

## Job description

Normal Computing | Build with Us Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London.

## The Role

As a Design-for-Test (DFT) Engineer at Normal, you will own the DFT architecture and implementation for our next-generation, physics-inspired ASICs, from early RTL design through tapeout and silicon bring-up. You will define and drive scan/ATPG, memory built-in self-test (MBIST), and boundary-scan strategies, working closely with RTL, verification, physical design, and silicon product engineering teams. This is a hands-on technical leadership role with end-to-end ownership of silicon testability. You will establish DFT methodologies, guide external implementation partners, and ensure our designs are ready for manufacturing test. You’ll work on unconventional computing architectures where testability must be considered from the beginning, with the opportunity to shape the DFT infrastructure for an entirely new class of silicon.

## What You Will Own

- DFT Architecture: Define and own chip-level DFT architecture, including scan insertion, ATPG, scan compression, MBIST, boundary scan/JTAG, and test access infrastructure.
- Implementation & Integration: Drive DFT insertion and integration across RTL, synthesis, and physical design, ensuring testability requirements are met without compromising power, performance, or area.
- Test Coverage & Signoff: Own DFT verification, ATPG pattern generation, fault coverage analysis, test-mode validation, and DFT signoff through tapeout.
- Manufacturing Test Readiness: Partner with the Head of Silicon Product Engineering to deliver production-ready test patterns and test collateral to our manufacturing partners, and documentation for ATE integration, silicon bring-up, and diagnosis.
- Methodology & Tooling: Establish scalable DFT flows, automation, and best practices using industry-standard EDA tools, supporting future ASIC programs.
- External Partner Collaboration: Define technical requirements, oversee contracted DFT work, and review deliverables to ensure quality and integration with Normal’s silicon development process.

What Makes You a Great Fit

- 7+ years of experience in DFT implementation for complex ASICs or SoCs, including successful tapeouts.
- Strong hands-on expertise in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation.
- Proven experience with MBIST, boundary scan/JTAG, and DFT integration across RTL and gate-level designs.
- Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus.
- Solid understanding of RTL design, synthesis, static timing analysis, and physical design considerations.
- Experience delivering manufacturing test patterns and collaborating with silicon product engineering or ATE teams.
- Strong scripting skills in Python, Tcl, or similar languages.
- Ability to independently own DFT architecture, drive cross-functional technical decisions, and communicate effectively across design, verification, and product engineering teams.

Bonus Points

- Experience establishing DFT architecture and methodology from the ground up for a new ASIC program.
- Familiarity with IEEE 1500, IEEE 1687 (IJTAG), hierarchical DFT, and advanced scan compression techniques.
- Experience with memory redundancy, built-in self-repair (BISR), silicon diagnosis, and yield improvement.
- Experience working with external DFT implementation partners or managing outsourced DFT deliverables.
- Exposure to AI accelerators, memory-intensive architectures, or unconventional computing systems.
- Experience using AI-assisted or agentic tools to automate silicon design and verification workflows.

## Equal Employment Opportunity Statement

Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our [Applicant Privacy Notice](https://normalcomputing.com/applicant-privacy-notice).

## About Normal Computing Corporation

## Company Overview
- **One-liner**: Normal Computing builds AI-accelerated EDA software and physics-based ASICs to enable ultra-efficient hardware for the AI era.
- **Entity Type**: Private (Series B; total funding $92.5M)
- **Headquarters**: New York, New York, USA
- **Founded**: 2022
- **Founders**: Faris Sbahi (CEO), Matthias Tan (Co-Founder), and team of former Google Brain/Google X engineers and scientists

## Core Business
- Primary industry: Semiconductor design (EDA) and custom silicon (ASICs), powered by AI and probabilistic computing.
- Target customers: Large semiconductor design and manufacturing institutions (B2B, enterprise).
- Mission: "Rewriting AI foundations to advance the frontier of reasoning and reliability in the physical world" and enabling a virtuous cycle of self-improving AI hardware.

## Products & Services
- **[Normal EDA](https://normalcomputing.com/)**: An AI-driven electronic design automation platform that understands design intent from specification documents, generates hierarchical test plans with traceability, creates SystemVerilog stimulus, runs simulations, and tracks coverage. It continuously learns from team feedback to accelerate verification for complex chip designs.
- **[Normal ASICs](https://normalcomputing.com/)**: Physics-based custom ASICs that relax traditional computing assumptions (stochastic, stateful, asynchronous) to unlock orders-of-magnitude more efficient compute. Designed to converge hardware with the physical dynamics of AI models.

## Market Standing
- **Valuation/Market Cap**: Not publicly disclosed.
- **Key Metric**: **Total Funding** – $92.5M across multiple rounds (Seed, Venture, Grant, Series B). Notable recent round: $50M led by **Samsung Catalyst** in March 2026 [normalcomputing.com](https://normalcomputing.com/).
- **Notable Investors**: Samsung Catalyst Fund, Intel Ignite, First Spark Ventures, Celesta Capital, ARIA. Also partners with Fraunhofer IESE (DRAMBench benchmark).
- **Growth Signals**: Headcount grew **196.3% YoY** to 54 employees; operates across 6 countries (US, UK, Denmark, Switzerland, India, Canada); actively building open-source tools (e.g., a Verilog simulator built with AI: 580K lines in 43 days).

## Competitive Advantages
- **Physics-First Approach**: Unlike traditional digital logic, Normal’s ASICs embrace stochastic, stateful, and asynchronous computing – aligning hardware with the physics of AI models for dramatic efficiency gains.
- **Full-Stack Co-Design**: The combination of AI-native EDA tools and custom silicon creates a closed loop where software and hardware are co-optimized, shortening time-to-market and enabling workload-specific ASICs.
- **Deep AI Heritage**: Founders and team hail from Google Brain and Google X, bringing deep expertise in probabilistic ML, quantum AI, and physical-world reasoning.

## Strategic Focus
- **Scaling EDA Adoption**: Expanding Normal EDA’s use among top semiconductor companies to "make chip design look more like software".
- **AI Hardware Energy Crisis**: Tackling soaring power demands of AI by delivering ultra-efficient ASICs that can be produced for every workload.
- **Open-Source & Research**: Building community trust through open benchmarks (DRAMBench) and tools (CIRCT-based verification), while advancing formal methods and AI-driven simulation.

## Why Work Here
- **Hybrid Workspace**: Flexible in-office collaboration at offices in **New York (Flatiron HQ)**, **San Francisco**, **London**, and **Copenhagen**. In-person collaboration is valued but with flexibility; free lunch, snacks, and beverages in office.
- **Lean, High-Impact Team**: Small team (54 employees) where every member drives significant impact, works directly with customers, and owns meaningful parts of the product.
- **Interdisciplinary Challenges**: Work spans AI, probabilistic software, hardware, physics, and full-stack engineering – ideal for curious, passionate problem-solvers.
- **Strong Growth Trajectory**: Rapid headcount growth (+196% YoY), recent $50M Series B, and partnerships with industry giants signal a well-funded, high-potential startup.

## Sources
1. [normalcomputing.com](https://normalcomputing.com/)
2. [normalcomputing.com/about](https://normalcomputing.com/about)
3. [linkedin.com/company/normal-computing-corporation](https://www.linkedin.com/company/normal-computing-corporation)
4. [builtin.com/company/normal-computing](https://builtin.com/company/normal-computing)
5. [jobs.ashbyhq.com/normalcomputing](https://jobs.ashbyhq.com/normalcomputing)

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