--- title: 'Hardware Engineer, Physical Design at Normal Computing Corporation' canonical: 'https://feeny.ai/job/hardware-engineer-physical-design-normal-computing-corporation-new-york-g5mh8xmxpc64' type: 'job' last_seen: '2026-09-10' --- # Hardware Engineer, Physical Design at Normal Computing Corporation - **Company:** Normal Computing Corporation - **Location:** New York, NY - **Employment:** full-time - **Work type:** onsite - **Posted:** 2026-07-31 - **Last confirmed live:** 2026-09-10 - **Apply:** https://jobs.ashbyhq.com/normalcomputing/d6869bfd-d8f8-4a3e-88ac-d65e870b57cb ## Job description Normal Computing | Build with Us Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul. ## The Role As a Physical Design Engineer at Normal, you will own the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout. Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems, you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams. You'll drive the full backend implementation flow—optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets. We are looking for a seasoned engineer who thrives in cross-functional environments and takes pride in tapeout-proven execution. The ideal candidate brings a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architectures. ## What You Will Own - Physical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R). - Timing Closure & STA: Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes. - Power, Area, and Signal Integrity: Drive physical optimization for power, performance, and area (PPA), as well as power integrity (IR/EM) and crosstalk analysis. - Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry. - Design & Floorplan Reviews: Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, pin assignments, and physical feasibility. - Tapeout & Post-Silicon Support: Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed. What Makes You a Great Fit - Tapeout Track Record: At least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes. - PD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure. - Backend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations. - Cross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility. Bonus Points - Experience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles. - Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration). - Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows. ## Equal Employment Opportunity Statement Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy. ## About Normal Computing Corporation ## Company Overview - **One-liner**: Normal Computing builds AI-accelerated EDA software and physics-based ASICs to enable ultra-efficient hardware for the AI era. - **Entity Type**: Private (Series B; total funding $92.5M) - **Headquarters**: New York, New York, USA - **Founded**: 2022 - **Founders**: Faris Sbahi (CEO), Matthias Tan (Co-Founder), and team of former Google Brain/Google X engineers and scientists ## Core Business - Primary industry: Semiconductor design (EDA) and custom silicon (ASICs), powered by AI and probabilistic computing. - Target customers: Large semiconductor design and manufacturing institutions (B2B, enterprise). - Mission: "Rewriting AI foundations to advance the frontier of reasoning and reliability in the physical world" and enabling a virtuous cycle of self-improving AI hardware. ## Products & Services - **[Normal EDA](https://normalcomputing.com/)**: An AI-driven electronic design automation platform that understands design intent from specification documents, generates hierarchical test plans with traceability, creates SystemVerilog stimulus, runs simulations, and tracks coverage. It continuously learns from team feedback to accelerate verification for complex chip designs. - **[Normal ASICs](https://normalcomputing.com/)**: Physics-based custom ASICs that relax traditional computing assumptions (stochastic, stateful, asynchronous) to unlock orders-of-magnitude more efficient compute. Designed to converge hardware with the physical dynamics of AI models. ## Market Standing - **Valuation/Market Cap**: Not publicly disclosed. - **Key Metric**: **Total Funding** – $92.5M across multiple rounds (Seed, Venture, Grant, Series B). Notable recent round: $50M led by **Samsung Catalyst** in March 2026 [normalcomputing.com](https://normalcomputing.com/). - **Notable Investors**: Samsung Catalyst Fund, Intel Ignite, First Spark Ventures, Celesta Capital, ARIA. Also partners with Fraunhofer IESE (DRAMBench benchmark). - **Growth Signals**: Headcount grew **196.3% YoY** to 54 employees; operates across 6 countries (US, UK, Denmark, Switzerland, India, Canada); actively building open-source tools (e.g., a Verilog simulator built with AI: 580K lines in 43 days). ## Competitive Advantages - **Physics-First Approach**: Unlike traditional digital logic, Normal’s ASICs embrace stochastic, stateful, and asynchronous computing – aligning hardware with the physics of AI models for dramatic efficiency gains. - **Full-Stack Co-Design**: The combination of AI-native EDA tools and custom silicon creates a closed loop where software and hardware are co-optimized, shortening time-to-market and enabling workload-specific ASICs. - **Deep AI Heritage**: Founders and team hail from Google Brain and Google X, bringing deep expertise in probabilistic ML, quantum AI, and physical-world reasoning. ## Strategic Focus - **Scaling EDA Adoption**: Expanding Normal EDA’s use among top semiconductor companies to "make chip design look more like software". - **AI Hardware Energy Crisis**: Tackling soaring power demands of AI by delivering ultra-efficient ASICs that can be produced for every workload. - **Open-Source & Research**: Building community trust through open benchmarks (DRAMBench) and tools (CIRCT-based verification), while advancing formal methods and AI-driven simulation. ## Why Work Here - **Hybrid Workspace**: Flexible in-office collaboration at offices in **New York (Flatiron HQ)**, **San Francisco**, **London**, and **Copenhagen**. In-person collaboration is valued but with flexibility; free lunch, snacks, and beverages in office. - **Lean, High-Impact Team**: Small team (54 employees) where every member drives significant impact, works directly with customers, and owns meaningful parts of the product. - **Interdisciplinary Challenges**: Work spans AI, probabilistic software, hardware, physics, and full-stack engineering – ideal for curious, passionate problem-solvers. - **Strong Growth Trajectory**: Rapid headcount growth (+196% YoY), recent $50M Series B, and partnerships with industry giants signal a well-funded, high-potential startup. ## Sources 1. [normalcomputing.com](https://normalcomputing.com/) 2. [normalcomputing.com/about](https://normalcomputing.com/about) 3. [linkedin.com/company/normal-computing-corporation](https://www.linkedin.com/company/normal-computing-corporation) 4. [builtin.com/company/normal-computing](https://builtin.com/company/normal-computing) 5. [jobs.ashbyhq.com/normalcomputing](https://jobs.ashbyhq.com/normalcomputing) ## Other roles at Normal Computing Corporation - [Hardware Engineer, System Design](https://feeny.ai/job/hardware-engineer-system-design-normal-computing-corporation-silicon-valley-ewmb4smy3n8k) — Silicon Valley - [Research Engineer, Agentic EDA](https://feeny.ai/job/research-engineer-agentic-eda-normal-computing-corporation-new-york-n9n5s5w4myky) — New York, NY - [Software Engineer, Terminal Interface](https://feeny.ai/job/software-engineer-terminal-interface-normal-computing-corporation-new-york-4wm9d2tfm0ja) — New York, NY - [Talent Operations Specialist](https://feeny.ai/job/talent-operations-specialist-normal-computing-corporation-silicon-valley-rj0rjeg87g4x) — Silicon Valley - [Thermodynamic Hardware Resident](https://feeny.ai/job/thermodynamic-hardware-resident-normal-computing-corporation-new-york-jg4avbjrxt43) — New York, NY - [AI Research Resident](https://feeny.ai/job/ai-research-resident-normal-computing-corporation-new-york-44frw5ybhavm) — New York, NY - [Hardware Engineer, Lead Architect](https://feeny.ai/job/hardware-engineer-lead-architect-normal-computing-corporation-silicon-valley-6fvq60qmptdw) — Silicon Valley - [Hardware Engineer, FPGA](https://feeny.ai/job/hardware-engineer-fpga-normal-computing-corporation-new-york-4v6epje87dne) — New York, NY - [Software Engineer, Agent Systems](https://feeny.ai/job/software-engineer-agent-systems-normal-computing-corporation-new-york-9mc74m2d7yp9) — New York, NY - [Research Engineer, Domain Scaling](https://feeny.ai/job/research-engineer-domain-scaling-normal-computing-corporation-new-york-f308m76kzev4) — New York, NY