---
title: 'Hardware Technical Program Manager at Efficient Computer'
canonical: 'https://feeny.ai/job/hardware-technical-program-manager-efficient-computer-san-jose-ca-or-pittsburgh-0q569t2yxvq8'
type: 'job'
last_seen: '2026-09-10'
---

# Hardware Technical Program Manager at Efficient Computer

- **Company:** Efficient Computer
- **Location:** San Jose CA OR Pittsburgh PA OR Austin, TX
- **Posted:** 2026-08-14
- **Last confirmed live:** 2026-09-10
- **Apply:** https://job-boards.greenhouse.io/efficientcomputer/jobs/4370905009

## Job description

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

We are looking for a Hardware Technical Program Manager to own the program end-to-end — from architecture freeze through RTL, verification, physical implementation, tapeout, bring-up, and production release.

You will be the operational center of the program: building and defending the schedule, driving the critical path, surfacing risk early, and making the tradeoff conversations happen before they become slips. You'll work daily with architecture, RTL design, DV/emulation, DFT, physical design, package, firmware, and the foundry/IP vendor ecosystem. Join our team and help us shape the future of computing at the edge and beyond!

## Key Responsibilities

Own the Program

- Own the   silicon schedule from architecture freeze through tapeout, bring-up, and production with  the schedule informed by customer requirements and internal functional leads.
- Drive the weekly execution cadence (program reviews, design reviews, tapeout readiness) and maintain a single source of truth for status, dependencies, and decisions.

Drive Cross-Functional Execution

- Coordinate handoffs across architecture, RTL, DV/emulation, DFT, physical design, IP, package, and software
- Manage the dependency chains hardware programs live and die on: IP delivery, PDK/library releases, EDA versions, and emulation capacity.
- Run the tapeout checklist and signoff matrix (timing, power, IR/EM, DRC/LVS, DFT coverage, ECO closure, GDS handoff), holding owners to closure criteria.
- Work with supply chain/logistics for: IP acquisition, silicon arrival, ATE/loadboard readiness, lab scheduling, bug triage, and ECO/respin decision support.

Manage Risk & Decisions

- Surface risk early with mitigation options and schedule impact quantified — late IP, coverage shortfalls, convergence misses, foundry slot changes.
- Facilitate PPA, schedule, and scope tradeoffs, and document what was decided, by whom, and why.

Coordinate Externally & Report Up

- Interface with foundry, OSAT, IP, and EDA partners on deliverables, technology file releases, mask slots, and escalations; support export control/ECCN compliance with legal and operations.
- Deliver crisp executive reporting — where the program stands, what's at risk, what decision is needed and by when — across distributed teams and time zones.
- Track resource allocation and NRE/mask/license/prototype budgets against program needs.

Required Qualifications

- B.S. in Electrical/Computer Engineering, Computer Science, or equivalent; M.S. or MBA a plus.
- 7+ years in semiconductor/hardware engineering or program management, including at least 2 full SoC/ASIC programs taken from concept through tapeout and silicon bring-up.
- Working fluency in the chip design flow: RTL, functional verification and coverage closure, DFT, synthesis, PnR, STA, physical signoff (DRC/LVS/IR/EM), GDSII handoff, and post-silicon validation.
- Demonstrated ability to build and defend a bottoms-up schedule with critical path analysis and dependency mapping.
- Track record influencing without authority — earning the technical credibility to push senior engineers on commitments and dates.
- Strong written and verbal communication; able to run a room of principal engineers and an exec review with equal effectiveness.
- Hands-on with program tooling: Jira, Confluence, MS Project/Smartsheet, and familiarity with the Synopsys/Cadence/Siemens EDA ecosystem.

Desired Qualifications & Experience Requirements

- Prior hands-on engineering experience in design, DV, or physical design before moving to program management.
- Experience on advanced or FinFET nodes (16/12/7nm or more advanced) and direct foundry engagement (TSMC preferred).
- Familiarity with AI/ML accelerators, dataflow or novel compute architectures..
- Experience managing emulation/FPGA prototyping programs and pre-silicon software enablement timelines.
- Exposure to package/board co-design programs (FC-BGA, WLCSP) and OSAT coordination.
- Experience with EVK/reference board programs and customer/FAE enablement schedules.
- Familiarity with quality and compliance frameworks relevant to the target market (automotive, industrial, or security certifications).

We offer a competitive salary for this role, generally ranging from $200,000 to $240,000, along with bonus, meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Why Join Efficient?

Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.

## About Efficient Computer

## Company Overview
- **One-liner**: Efficient Computer is building the world’s most energy-efficient general-purpose processor by combining a novel Fabric architecture with an intuitive compiler, targeting edge AI, industrial automation, space/defense, and beyond.
- **Entity Type**: Private (Series A)
- **Headquarters**: Pittsburgh, Pennsylvania, United States
- **Founded**: 2022
- **Founders**: Brandon Lucia (CEO) and Nathan Beckmann (Chief Architect)

## Core Business
- Primary industry/industries: Semiconductor / Computer Hardware / AI Chips
- Target customers: B2B – OEMs and systems integrators in edge AI, industrial automation, satellite/space, automotive, defense, and consumer electronics
- Mission or purpose statement: To set a new standard for energy efficiency in general-purpose computation, enabling applications that are infeasible today due to energy constraints. [efficient.computer/about](https://www.efficient.computer/about)

## Products & Services
- **[Electron E1 Processor]**: A general-purpose processor featuring the proprietary Fabric architecture and 4MB of on-chip MRAM. It replaces von Neumann execution with a spatial dataflow model, delivering up to 1 TOPS/W and scaling from 5.4 GOPS to 21.6 GOPS. Designed for always-on AI inference at the edge. [efficient.computer/technology](https://www.efficient.computer/technology)
- **[effcc Compiler]**: A drop-in replacement for GCC/Clang that automatically extracts parallelism from C, C++, and TFLite code and maps it to the Fabric architecture. Provides ultra-fast compilation times and a GDB-compatible debugging experience. [efficient.computer/technology](https://www.efficient.computer/technology)
- **[Fabric Architecture]**: The core technology – a tiled grid of reconfigurable compute nodes that eliminates instruction fetch and decode overhead, achieving 10–100× energy efficiency gains over traditional CPUs and GPUs. [efficient.computer](https://www.efficient.computer/)

## Market Standing
- **Valuation/Market Cap**: Not disclosed (private company)
- **Key Metric**: Total Funding – $70.0M across 3 rounds (Seed and Series A)
- **Notable Investors/Partners**: Triatomic Capital (led Series A), Eclipse (led Seed round). Key advisors include Alex Hawkinson (founder of SmartThings and BrightAI). [linkedin.com/company/efficientcomputer](https://www.linkedin.com/company/efficientcomputer)
- **Growth Signals**: 
  - 46 employees (+79.4% YoY, +27 people)
  - 13,966 LinkedIn followers (+180.4% yearly growth)
  - First silicon product (Electron E1) delivered to customers in mid-2025, ramping to volume distribution in 2026
  - Customer traction in physical AI, space/defense, automotive, and consumer products

## Competitive Advantages
- **Fabric Architecture**: A fundamentally new compute paradigm that is 10–100× more energy-efficient than traditional CPUs/GPUs for general-purpose workloads, including AI inference.
- **Full Programmability**: Unlike specialized accelerators that only optimize isolated kernels, the Fabric architecture accelerates entire applications without requiring code rewrites.
- **Proven Silicon**: Two silicon implementations (Electron E0 prototype and Electron E1 product) are already in customer hands.
- **World-Class Team**: Founders and key engineers are leading computer architects from Carnegie Mellon University, with deep expertise in efficient computing.

## Strategic Focus
- Scale the Electron E1 processor into high-volume production and distribution (targeting 2026).
- Expand into multiple verticals: physical AI, industrial automation, space/satellite, defense, automotive, and consumer electronics.
- Continue developing the effcc compiler ecosystem to support more frameworks and languages.
- Grow the engineering team, particularly in physical design, verification, architecture, and software optimization.

## Why Work Here
- **Cutting-Edge Technology**: Work on a novel processor architecture that redefines energy efficiency for the AI era.
- **Strong Growth Trajectory**: The company is scaling rapidly (nearly 80% headcount growth YoY) with a clear product-market fit and customer traction.
- **Engineering-Centric Culture**: 43% of the workforce is in technical roles, with a focus on computer architecture, compiler design, and silicon engineering.
- **Compensation & Benefits**: Competitive base salaries, meaningful startup equity, 401k matching, and a choose-your-own-adventure equipment allowance. [efficient.computer/about](https://www.efficient.computer/about)
- **Work Locations**: Offices in Pittsburgh, PA; San Jose, CA; and Austin, TX. Roles are on-site/hybrid at these hubs.
- **Values-Driven**: The company emphasizes integrity, impact, and accountability. [efficient.computer/about](https://www.efficient.computer/about)
- **Open Roles (as of mid-2026)**: 7 active positions including Design Verification Manager, Hardware Infrastructure & CI/CD Engineer, Senior Product Managers (Hardware/Software), Computer Architect, and Lead Physical Design Engineer.

## Sources
1. [efficient.computer](https://www.efficient.computer/)
2. [efficient.computer/about](https://www.efficient.computer/about)
3. [efficient.computer/technology](https://www.efficient.computer/technology)
4. [linkedin.com/company/efficientcomputer](https://www.linkedin.com/company/efficientcomputer)
5. [job-boards.greenhouse.io/efficientcomputer](http://job-boards.greenhouse.io/efficientcomputer)

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