---
title: 'Junior Emulation Engineer at Celero Communications, Inc.'
canonical: 'https://feeny.ai/job/junior-emulation-engineer-celero-communications-inc-cordoba-mr1rgy0be981'
type: 'job'
last_seen: '2026-11-06'
---

# Junior Emulation Engineer at Celero Communications, Inc.

- **Company:** Celero Communications, Inc.
- **Location:** Cordoba, Argentina
- **Posted:** 2026-10-27
- **Last confirmed live:** 2026-11-06
- **Apply:** https://job-boards.greenhouse.io/celerocommunicationsinc/jobs/4470032009

## Job description

Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure. We recently announced a $275M Series C following the validation of the industry’s first 2nm coherent DSP silicon. Bloomberg also reported that Alphabet’s CapitalG has backed Celero at a $3B valuation. As we continue to grow, we’re hiring exceptional talent across the United States, Canada, and Argentina for a variety of exciting opportunities.

We are seeking a motivated Junior Emulation Engineer to join our pre-silicon verification team. This is an excellent opportunity for recent graduates and early-career engineers to build hands-on experience bringing up complex SoC designs on hardware emulation platforms. In this role, you will help compile, run, and debug RTL on emulation systems, supporting early validation of hardware and firmware ahead of tape-out. You will work closely with RTL design, verification, and firmware teams, learn from senior engineers, and grow into an independent contributor on next-generation semiconductor products.

## Key Responsibilities

- Emulation Bring-Up: Support compilation, partitioning, and bring-up of RTL designs on hardware emulation platforms.
- Environment Support: Assist in building and maintaining emulation environments, including testbenches, transactors, and run configurations.
- Debug & Triage: Analyze waveforms, logs, and traces to isolate failures, and work with RTL and verification engineers to root-cause issues.
- Automation: Develop and maintain scripts in Python, Tcl, Perl, or shell to automate builds, regressions, and reporting.
- Firmware & Software Enablement: Help run pre-silicon firmware and software workloads on emulation to validate functionality before silicon.
- Documentation & Growth: Document findings, flows, and best practices, and actively learn emulation methodologies from senior team members.

## Key Qualifications

- Bachelor’s degree in Electronic, Electrical, or Computer Engineering (or a related field), completed or expected within the next 6–12 months.
- 0–2+ years of relevant experience; internships, thesis work, and academic or personal projects in digital design, verification, or FPGA are welcome.
- Digital Design Fundamentals: Solid understanding of combinational and sequential logic, FSMs, clock domains, and basic timing concepts.
- HDL Knowledge: Working knowledge of Verilog/SystemVerilog; able to read RTL and debug simple design or testbench issues.
- Scripting & Linux: Basic proficiency in Python, Tcl, Perl, or shell scripting, and comfort working in a Linux command-line environment.
- Communication: Professional English (written and spoken) for collaboration with global teams.
- Nice to Have: Exposure to emulation or FPGA prototyping tools (e.g., Cadence Palladium/Protium, Synopsys ZeBu, Siemens Veloce, Vivado/Quartus), UVM or SystemVerilog assertions, SoC basics (AXI/AMBA, ARM/RISC-V, DDR, PCIe), and Git or CI tools.
- This is an on-site position. Qualified candidates must be willing to relocate to Cordoba.

## About Celero Communications, Inc.

## Company Overview
- **One-liner**: Celero Communications develops advanced coherent DSP solutions that enable high-bandwidth, low-power optical connectivity for AI infrastructure, eliminating distance bottlenecks in data centers.
- **Entity Type**: Private (Series B; total funding $148.4M per LinkedIn, $140M per company press release)
- **Headquarters**: Irvine, California, USA
- **Founded**: 2024
- **Founders**: Nariman Yousefi (CEO, President & Co-founder) and Oscar Agazzi (CTO & Co-founder)

## Core Business
- **Primary industry**: Semiconductor manufacturing / optical networking for AI infrastructure
- **Target customers**: B2B – hyperscale data centers, AI cloud providers, and large-scale accelerated computing clusters
- **Mission**: “Deliver the optical performance and scalability needed for the next generation of accelerated computing” [celero.inc](https://celero.inc/about/)

## Products & Services
- **Coherent DSP Platform**: A digital signal processor that provides light-speed performance, bandwidth efficiency, and scalable optical links for AI accelerators, servers, and clusters. The technology is described as 100x more efficient than conventional optical transmission and is designed for interoperability across diverse AI and cloud platforms. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/)

## Market Standing
- **Valuation**: Not publicly disclosed
- **Key Metric**: Total funding of **$148.4 million** (Seed $8.4M led by Sutter Hill Ventures; Venture Round $40M; Series B $100M led by CapitalG) [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Notable Investors/Partners**: Sutter Hill Ventures (lead seed & Series A), CapitalG (lead Series B), plus other undisclosed investors in venture round [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Growth Signals**: Founded in 2024, already employs **93 people** with a monthly headcount growth of **+9.3%**. Operates design centers in Irvine (CA), Ottawa (Canada), and Córdoba (Argentina). [linkedin.com](https://www.linkedin.com/company/celero-communications)

## Competitive Advantages
- **Founding team** consists of industry pioneers from Marvell, Inphi, Broadcom, and ClariPhy with decades of experience in analog design, digital signal processing, and optical networking. [celero.inc](https://celero.inc/about/)
- **Coherent DSP technology** that eliminates distance bottlenecks, delivering 100x more efficient optical transmission for scale-across AI infrastructure. [celero.inc](https://celero.inc/)
- **System flexibility and interoperability** across diverse AI and cloud platforms, making it easier for data centers to adopt. [celero.inc](https://celero.inc/)

## Strategic Focus
- **Current priorities**: Scaling AI infrastructure connectivity by delivering high-bandwidth, low-power optical links; expanding engineering teams across all design centers; and building energy-efficient systems that redefine how data centers connect. [celero.inc](https://celero.inc/careers/)

## Why Work Here
- **Culture**: Described as driven by curiosity, precision, and the challenge of making AI systems faster and more energy-efficient. Employees collaborate with global experts in coherent DSP and optical engineering. [celero.inc](https://celero.inc/careers/)
- **Work model**: On-site/hybrid at three locations – Irvine, CA (HQ); Ottawa, Canada; and Córdoba, Argentina. Multiple engineering roles (Analog Design, ASIC, DSP, Firmware, Verification) are posted with specific location requirements. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc)
- **Notable perks**: Opportunity to work on next-generation AI infrastructure technology alongside industry pioneers. The company emphasizes building scalable, energy-efficient systems and offers roles across R&D, operations, and manufacturing. [celero.inc](https://celero.inc/careers/)

## Sources
1. [celero.inc](https://celero.inc/) – Company homepage and product description
2. [celero.inc](https://celero.inc/about/) – About page (founding, leadership, mission)
3. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/) – Press release on $140M funding
4. [linkedin.com](https://www.linkedin.com/company/celero-communications) – LinkedIn company page (funding details, headcount, locations, employee breakdown)
5. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc) – Careers page (open positions, locations)

## Other roles at Celero Communications, Inc.

- [Office Manager](https://feeny.ai/job/office-manager-celero-communications-inc-san-jose-cn78s1p95vfp) — San Jose, CA
- [Senior ASIC Design Engineer - DSP/Analog/SerDes](https://feeny.ai/job/senior-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-ottawa-x63zcvwcjacj) — Ottawa, Canada
- [Senior ASIC Design Engineer - DSP/Analog/SerDes](https://feeny.ai/job/senior-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-irvine-cetabymy86nx) — Irvine, CA
- [Senior ASIC Design Engineer - DSP/Analog/SerDes](https://feeny.ai/job/senior-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-san-jose-aybnp6fps5vc) — San Jose, CA
- [Post-Silicon Validation Engineer (Multiple Levels)](https://feeny.ai/job/post-silicon-validation-engineer-multiple-levels-celero-communications-inc-wrpm0f2vanb5) — Irvine CA OR Ottawa Ontario, Canada
- [Principal Optical Systems Engineer](https://feeny.ai/job/principal-optical-systems-engineer-celero-communications-inc-ottawa-5esg1r55angb) — Ottawa, Canada
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-abktjq9g2jgw) — Ottawa, Canada
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-4kasvranjrvf) — San Jose, CA
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-vnzcs82knnj6) — Irvine, CA
- [High-Speed Analog Layout Design Engineer](https://feeny.ai/job/high-speed-analog-layout-design-engineer-celero-communications-inc-cordoba-k9yg56pm5h0s) — Córdoba, Argentina