---
title: 'Lead Physical Design Engineer at Fractile'
canonical: 'https://feeny.ai/job/lead-physical-design-engineer-fractile-london-63c0jjnr1qp4'
type: 'job'
last_seen: '2026-09-11'
---

# Lead Physical Design Engineer at Fractile

- **Company:** Fractile
- **Location:** London, United Kingdom
- **Posted:** 2026-05-08
- **Last confirmed live:** 2026-09-11
- **Apply:** https://job-boards.eu.greenhouse.io/fractile/jobs/4861346101

## Job description

Lead Physical Design Engineer

## About Fractile

Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.

The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

- Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
- Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
- Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
- Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
- Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
- Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
- Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
- Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
- Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

- Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
- Strong proficiency in EDA tools for place & route, STA, and sign-off.
- Solid understanding of CMOS technology, semiconductor physics, and process limitations.
- Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
- Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
- Proficiency in scripting languages like TCL, Perl, or Python for automation.
- Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
- Experience in high-performance computing (HPC), AI accelerators, or networking chips.
- Experience or strong interest in leveraging advanced AI tools and models within engineering workflows

## What We Offer

- Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role.
- Equity & Ownership: meaningful equity so everyone shares in the value creation.
- Benefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance.
- Diverse & fun office: we believe the hardest problems get solved by the broadest range of minds. We are committed to Equal Employment Opportunity through attracting and retaining a diverse team and building an inclusive environment.

Fractile is seeking to increase the clock speed of global progress, one chip at a time. We’ve recently raised $220M from investors including Founders Fund and Accel and our most important work lies ahead. Join us!

Export controls

Our work involves technologies subject to UK, US and other international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.

## About Fractile

## Company Overview
- **One-liner**: Fractile builds chips, systems, and software to radically improve the speed and cost of running frontier AI inference, targeting up to 25x faster performance at 1/10th the cost.
- **Entity Type**: Private (Series B)
- **Headquarters**: London & Bristol, United Kingdom
- **Founded**: 2022
- **Founders**: Walter Goodwin (CEO)

## Core Business
- **Primary industry**: AI hardware acceleration, computer hardware manufacturing
- **Target customers**: B2B – enterprise cloud providers, AI labs, and organizations running large-scale frontier model inference
- **Mission**: "Build the engine that can power the next generation of AI" by removing every bottleneck to the fastest possible inference of the largest transformer networks.

## Products & Services
- **Fractile AI Accelerator Processor**: A new class of processor that physically interleaves memory and compute to deliver low latency and high throughput simultaneously. Designed to serve thousands of tokens per second to thousands of concurrent users at a fraction of the power and cost of existing hardware. (Hardware + full-stack software)

## Market Standing
- **Valuation/Market Cap**: Not publicly disclosed
- **Key Metric**: Total funding of **$243.8M** (per LinkedIn) or **$266.4M** (per CB Insights – conflicting reports); most recent round was a **$220M Series B** in May 2026 led by Accel, with participation from Factorial Funds and Founders Fund.
- **Notable Investors/Partners**: Accel, Factorial Funds, Founders Fund (Peter Thiel), Oxford Science Enterprises, Kindred Capital, Patrick Gelsinger (former Intel CEO), ARIA
- **Growth Signals**: Headcount grew **+171.4% YoY** to 66 employees; **+56.8% monthly LinkedIn follower growth**; **53 active job postings** (up 2550% year-over-year); expanding into a new hardware test site and growing offices in Bristol and London.

## Competitive Advantages
- **Full-stack approach**: Team spans transistor-level circuit design up to cloud inference server logic, enabling tight integration across silicon, systems, and software.
- **Novel architecture**: Interleaving memory and compute solves the memory-wall bottleneck that limits existing hardware, allowing simultaneous low latency and high throughput for frontier models.
- **Focus on inference (not training):** Addresses the exploding demand for token processing (10x/year growth) with a purpose-built solution for inference workloads.

## Strategic Focus
- Scale the engineering team across hardware and software disciplines (Rust, ML runtime, silicon design, board test, manufacturing operations).
- Expand physical infrastructure (new hardware test site in Bristol).
- Deploy the first generation of processors to enable new workloads like long-context autonomous agents and real-time AI reasoning.

## Why Work Here
- **Culture**: Deeply collaborative, no silos, no handoffs – engineers work across the full stack from transistor to cloud in a flat, mission-driven environment.
- **Locations**: Modern, open-plan offices in central Bristol and central London with excellent transport links.
- **Growth**: High-growth startup with strong funding and a clear trajectory; opportunity to work on one of the most impactful technical challenges in AI.
- **Team**: Composed of world-class technologists, many from companies like Graphcore, Imagination Technologies, and Cisco.
- **Remote/Hybrid**: Not explicitly stated, but hardware-focused roles (silicon, test, manufacturing) suggest a strong on-site presence; software roles may offer flexibility.

## Sources
1. [fractile.ai](https://www.fractile.ai/) – Company website
2. [fractile.ai/about](https://www.fractile.ai/about) – About page, team, culture
3. [fractile.ai/jobs](https://www.fractile.ai/jobs) – Open positions and work philosophy
4. [uk.linkedin.com/company/fractile](https://uk.linkedin.com/company/fractile) – LinkedIn company page (funding, headcount, growth)
5. [cbinsights.com/company/fractile](https://www.cbinsights.com/company/fractile) – CB Insights profile (funding details, patents, headquarters)

## Other roles at Fractile

- [Infrastructure Software Engineering – Platform & Build 1](https://feeny.ai/job/infrastructure-software-engineering-platform-build-1-fractile-london-8py3rwe9a22a) — London, United Kingdom
- [Lead RTL Designer (PPA Experience)](https://feeny.ai/job/lead-rtl-designer-ppa-experience-fractile-london-v7tb393epzj8) — London, United Kingdom
- [Infrastructure Engineer (Linux)](https://feeny.ai/job/infrastructure-engineer-linux-fractile-london-wf39d8qcrs18) — London, United Kingdom / Bristol, United Kingdom
- [Product & Yield Engineer (Data-focused)](https://feeny.ai/job/product-yield-engineer-data-focused-fractile-london-01d227xazs8j) — London, United Kingdom
- [Product & Yield Engineer (Data-focused)](https://feeny.ai/job/product-yield-engineer-data-focused-fractile-bristol-0f9p7n1xjmmp) — Bristol, United Kingdom
- [DRAM Product Engineer](https://feeny.ai/job/dram-product-engineer-fractile-bristol-nnksz0zaqnsd) — Bristol, United Kingdom
- [Engineering Manager - Compilers](https://feeny.ai/job/engineering-manager-compilers-fractile-london-7jmh8904r5mz) — London, United Kingdom / Bristol, United Kingdom
- [Developer Experience / DevEx](https://feeny.ai/job/developer-experience-devex-fractile-london-4r0qtvaa55gk) — London, United Kingdom
- [Member of Technical Staff - Security Engineering](https://feeny.ai/job/member-of-technical-staff-security-engineering-fractile-london-kdbxzfb0y24f) — London, United Kingdom / Bristol, United Kingdom
- [Developer Experience / DevEx](https://feeny.ai/job/developer-experience-devex-fractile-bristol-2wmefvt5bhap) — Bristol, United Kingdom