---
title: 'Manager, ATE Test Engineering at Astera Labs'
canonical: 'https://feeny.ai/job/manager-ate-test-engineering-astera-labs-san-jose-california-13hyv82aazff'
type: 'job'
last_seen: '2026-09-11'
---

# Manager, ATE Test Engineering at Astera Labs

- **Company:** Astera Labs
- **Location:** San Jose California, United States
- **Posted:** 2026-08-28
- **Last confirmed live:** 2026-09-11
- **Apply:** https://job-boards.greenhouse.io/asteralabs/jobs/4728527005

## Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/).

## Role Overview

Astera Labs is seeking a Manager, ATE Test Engineering to lead our Test engineering organization in San Jose, CA. This is a critical leadership role responsible for driving next-generation high-speed, high-performance products from silicon bring-up through high-volume manufacturing in advanced process nodes.

Astera Labs is looking to build and scale the Test Engineering team responsible for developing scalable ATE solutions for complex mixed-signal silicon products and high-speed products that power next-generation AI infrastructure. You will shape test strategy, guide execution across wafer sort and final test, and ensure products move confidently from design through silicon bring-up and high-volume production.

This is an opportunity to combine technical depth with engineering leadership at a hyper-growth connectivity company. Your decisions will directly influence product quality, manufacturing readiness, and customer experience. You will partner across design, DFT, product engineering, operations, and manufacturing to improve coverage, quality, cost, and test time as Astera Labs scales purpose-built connectivity for rack-scale AI systems.

## Key Responsibilities

- Team Leadership & Organization Building
- Build, mentor, and lead a high-performing team of ATE Test engineers owning a diverse portfolio of connectivity products purpose-built for AI infrastructure
- Establish scalable processes, best-known methods (BKMs), and operational excellence frameworks as the organization grows
- Make sound technical and organizational decisions in a fast-paced, dynamic environment with competing priorities
- Test Strategy and Product Ownership
- Define end-to-end ATE test strategies and plans for high-speed connectivity products from design engagement through high-volume production.
- Establish coverage, quality, test-time, cost, and yield objectives, and drive measurable improvements across the product lifecycle.
- Lead silicon and ATE bring-up, bench-to-ATE correlation, production release, and ongoing test optimization.
- ATE Hardware, Software, and Silicon Validation
- Guide to tester platform selection and development of load boards, interface hardware, and test solutions for wafer sort and final test.
- Direct ATE program development, pattern implementation, debug, and resource optimization on Advantest 93k or Teradyne platforms.
- Drive characterization and production test of high-speed SerDes and mixed-signal interfaces, including PCIe, Ethernet, DDR, NVMe, and USB.
- Partner with DFT and design teams to implement SCAN, MBIST, SerDes, and functional test methods that maximize defect and parametric coverage.
- Cross-Functional Leadership and Manufacturing Execution
- Build alignment with design, DFT, product engineering, operations, and external manufacturing partners on readiness, risk, and release decisions.
- Develop technical talent, set priorities, and create a culture of ownership, rigorous execution, and continuous improvement.
- Use data from production, lab equipment, protocol analyzers, oscilloscopes, and manufacturing systems to resolve issues and improve product quality.

## Basic Qualifications

- Bachelor's degree in electrical engineering or related technical field.
- 8+ years of experience developing and supporting ATE test solutions for complex High-speed products or SoC products.
- 3+ years of managerial experience building and leading Test engineering team
- Working knowledge of high-speed protocols and physical-layer behavior, including PCIe, Ethernet, DDR, NVMe, or USB.
- Experience with ATE program development, silicon bring-up, bench-to-ATE correlation, production debug, and test-time optimization.
- Ability to communicate clearly, manage competing priorities, and partner effectively across technical and manufacturing organizations.

## Preferred Qualifications

- Master’s or PhD in Electrical Engineering or related field.
- Experience leading wafer-sort and final-test hardware development, including high-speed load-board design.
- Strong knowledge of DFT techniques such as SCAN, MBIST, SerDes, and functional test, plus control interfaces including I2C, I3C, SPI, MDIO, and JTAG.
- Experience testing high-speed SerDes operating at 16 Gbps or higher, including external loopback at wafer sort.
- Proficiency in C/C++ or Python for ATE programming, data processing, and automation; familiarity with modern databases and RF testing on ATE platforms.
- Demonstrated ability to develop engineers, influence cross-functional decisions, and deliver results in a fast-paced, high-growth environment.

Salary range is $195,000 to $250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonuses, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## About Astera Labs

## Company Overview
- **One-liner**: Astera Labs designs and delivers semiconductor-based connectivity solutions purpose-built to unleash the full potential of cloud and AI infrastructure.
- **Entity Type**: Public (Nasdaq: ALAB)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2017
- **Founders**: Jitendra Mohan, Sanjay Gajendra, Casey Morrison

## Core Business
- **Primary industry**: Semiconductor manufacturing / AI infrastructure connectivity
- **Target customers**: B2B, primarily hyperscale cloud providers and system OEMs (e.g., NVIDIA, AMD, Intel)
- **Mission statement**: To innovate, design, and deliver semiconductor-based connectivity solutions that are purpose-built to unleash the full potential of cloud and AI infrastructure.

## Products & Services
- **Aries PCIe®/CXL™ Smart DSP Retimers**: Silicon ICs, boards, and modules that digitally recover degraded high-speed signals to extend reach and enable higher PCIe/CXL data bandwidth between compute, storage, and network controllers.
- **Taurus Ethernet Smart Cable Modules™**: Hardware modules that increase network connectivity bandwidth between servers and switches over copper media, removing rack-level Ethernet bottlenecks.
- **Leo CXL Memory Connectivity Controllers**: ICs and boards that expand, share, and pool DRAM memory to overcome processor memory bandwidth bottlenecks for AI workloads.
- **Scorpio Smart Fabric Switches**: A family of PCIe 6 fabric switches ranging from 32 to 320 lanes, including the new 320-lane Scorpio X-Series Fabric Switch for AI scale-up fabrics.
- **COSMOS Software Suite**: A connectivity system management and optimization software that enables configuration, monitoring, troubleshooting, and predictive analytics for all Astera Labs products.

## Market Standing
- **Market Cap**: ~$11.6 billion (as of mid-2026)
- **Key Metric - Revenue**: $35 million (annual, reported)
- **Key Metric - Operating Income**: $173.4 million (2025)
- **Key Metric - Net Income**: $219.1 million (2025)
- **Total Funding**: ~$810.75 million (pre-IPO), with Series C ($50M, led by Fidelity) and Series D ($150M, led by Fidelity)
- **IPO Date**: March 20, 2024
- **Notable Investors/Partners**: Fidelity, NVIDIA, Advanced Micro Devices, Intel, major hyperscalers
- **Growth Signals**: 92% YoY headcount growth (675 employees); 144 active job postings (+260% YoY); expanded Taiwan operations with a new Cloud-Scale Interop Lab in 2026; shipping millions of devices across all major hyperscalers; 300+ design wins.

## Competitive Advantages
- **First-to-market innovation**: Pioneered first-to-market PCIe, Ethernet, and CXL connectivity products.
- **Patented software-defined platform approach**: Differentiates via a platform that combines silicon hardware with embedded COSMOS software, enabling flexibility, observability, and predictive analytics.
- **Deep hyperscaler relationships**: Trusted partner to the world’s largest cloud providers, with proven interoperability validated in their own Cloud-Scale Interop Lab.
- **Broad product portfolio**: Covers PCIe retimers, Ethernet cable modules, CXL memory controllers, and fabric switches—addressing the full spectrum of AI connectivity bottlenecks.
- **Strong IP and engineering talent**: 443 employees in technical roles; talent sourced from Intel (65), Marvell (37), Texas Instruments (40), AMD (22), and NVIDIA.

## Strategic Focus
- **Scaling AI infrastructure**: Expanding product portfolio and global footprint (12 countries) to meet surging demand for rack-scale AI.
- **Open standards leadership**: All products are grounded in open standards (PCIe, CXL, Ethernet), ensuring interoperability and broad adoption.
- **Taiwan expansion**: Growing engineering presence and Interop Lab in Taiwan to strengthen integration with leading AI platform providers and system manufacturers.
- **Continued innovation**: Shipping the new 320-lane Scorpio X-Series Fabric Switch and expanding the COSMOS software suite for fleet-level management and optimization.

## Why Work Here
- **Culture**: Described as collaborative, ownership-driven, and focused on solving complex problems together. The company emphasizes diversity and inclusion as drivers of creativity and innovation.
- **Growth**: Astera Labs supports non-linear career growth—employees can deepen expertise (“scale up”) or broaden into new areas (“scale out”). 92% YoY headcount growth signals rapid expansion and opportunity.
- **Remote/Hybrid**: Not explicitly stated, but global operations across 12 countries (including India, Canada, Israel, Taiwan, Vietnam) suggest a flexible, distributed work model.
- **Benefits**: Competitive medical, dental, and vision plans; flexible time off; family planning and parental leave; 401K and retirement plans.
- **Engineering culture**: Strong focus on cutting-edge semiconductor and AI infrastructure technology. High concentration of senior (24%) and specialist (19%) talent. Active internship and new graduate programs.
- **Employee ratings**: 4.5/5.0 on LinkedIn (124 reviews), with high marks for compensation (4.6), culture (4.4), and career development (4.4).

## Sources
1. [Astera Labs Careers Page](https://www.asteralabs.com/careers/)
2. [Astera Labs Official Website](https://www.asteralabs.com/)
3. [Astera Labs LinkedIn](https://www.linkedin.com/company/astera-labs)
4. [Astera Labs Products Page](https://www.asteralabs.com/products/)
5. [Astera Labs S-1 Filing (SEC)](https://ir.asteralabs.com/static-files/7103a4cb-aa6b-4f11-a4b0-f179cd4c5bee)

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