---
title: 'Manager, Digital Design at Astera Labs'
canonical: 'https://feeny.ai/job/manager-digital-design-astera-labs-san-jose-california-v98047j0w79e'
type: 'job'
last_seen: '2026-09-18'
---

# Manager, Digital Design at Astera Labs

- **Company:** Astera Labs
- **Location:** San Jose California, United States
- **Posted:** 2026-09-17
- **Last confirmed live:** 2026-09-18
- **Apply:** https://job-boards.greenhouse.io/asteralabs/jobs/4727604005

## Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/).

## Role Overview

As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance, quality, and schedule objectives.

This is an opportunity to influence the development of purpose-built connectivity products at a hyper-growth company, establish scalable design practices, and help deliver silicon that advances the next generation of AI systems.

## Key Responsibilities

- End-to-End Chip Development
- Lead digital design execution from product requirements and architecture through RTL, verification, tape-out, and production shipment.
- Drive delivery of at least two complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability.
- Partner with architecture and system teams to translate PCIe & CXL, UAL, ethernet requirements into robust, scalable digital implementations.
- RTL Quality and Tape-Out Readiness
- Set expectations for high-quality front-end RTL that enables efficient synthesis, timing closure, physical implementation, and smooth tape-out.
- Establish and maintain design checklists, review gates, coding standards, and signoff criteria across the digital design lifecycle.
- Resolve design, performance, power, area, clocking, and integration issues in partnership with verification, physical design, DFT, and validation teams.
- Team and Cross-Functional Leadership
- Lead, mentor, and develop a team of 6–8 digital design engineers, fostering technical excellence, accountability, and effective collaboration.
- Influence cross-functional development decisions and align engineering teams around quality, risk reduction, and on-time execution.
- Communicate technical status, tradeoffs, dependencies, and mitigation plans to engineering and program leadership.

## Basic Qualifications

- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations.
- 3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design.
- Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexity.
- Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality.
- Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations.

## Preferred Qualifications

- Expertise in RTL quality methodologies, design reviews, lint, clock-domain and reset-domain considerations, synthesis, timing, and signoff readiness.
- Experience defining or improving design checklists, development flows, quality gates, and cross-functional tape-out processes.
- Building design blocks with large physical floorplan sizes is a plus
- Track record of balancing performance, power, area, schedule, and risk across large SoC or ASIC programs.
- Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.

Salary range is $216,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

## About Astera Labs

## Company Overview
- **One-liner**: Astera Labs designs and delivers semiconductor-based connectivity solutions purpose-built to unleash the full potential of cloud and AI infrastructure.
- **Entity Type**: Public (Nasdaq: ALAB)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2017
- **Founders**: Jitendra Mohan, Sanjay Gajendra, Casey Morrison

## Core Business
- **Primary industry**: Semiconductor manufacturing / AI infrastructure connectivity
- **Target customers**: B2B, primarily hyperscale cloud providers and system OEMs (e.g., NVIDIA, AMD, Intel)
- **Mission statement**: To innovate, design, and deliver semiconductor-based connectivity solutions that are purpose-built to unleash the full potential of cloud and AI infrastructure.

## Products & Services
- **Aries PCIe®/CXL™ Smart DSP Retimers**: Silicon ICs, boards, and modules that digitally recover degraded high-speed signals to extend reach and enable higher PCIe/CXL data bandwidth between compute, storage, and network controllers.
- **Taurus Ethernet Smart Cable Modules™**: Hardware modules that increase network connectivity bandwidth between servers and switches over copper media, removing rack-level Ethernet bottlenecks.
- **Leo CXL Memory Connectivity Controllers**: ICs and boards that expand, share, and pool DRAM memory to overcome processor memory bandwidth bottlenecks for AI workloads.
- **Scorpio Smart Fabric Switches**: A family of PCIe 6 fabric switches ranging from 32 to 320 lanes, including the new 320-lane Scorpio X-Series Fabric Switch for AI scale-up fabrics.
- **COSMOS Software Suite**: A connectivity system management and optimization software that enables configuration, monitoring, troubleshooting, and predictive analytics for all Astera Labs products.

## Market Standing
- **Market Cap**: ~$11.6 billion (as of mid-2026)
- **Key Metric - Revenue**: $35 million (annual, reported)
- **Key Metric - Operating Income**: $173.4 million (2025)
- **Key Metric - Net Income**: $219.1 million (2025)
- **Total Funding**: ~$810.75 million (pre-IPO), with Series C ($50M, led by Fidelity) and Series D ($150M, led by Fidelity)
- **IPO Date**: March 20, 2024
- **Notable Investors/Partners**: Fidelity, NVIDIA, Advanced Micro Devices, Intel, major hyperscalers
- **Growth Signals**: 92% YoY headcount growth (675 employees); 144 active job postings (+260% YoY); expanded Taiwan operations with a new Cloud-Scale Interop Lab in 2026; shipping millions of devices across all major hyperscalers; 300+ design wins.

## Competitive Advantages
- **First-to-market innovation**: Pioneered first-to-market PCIe, Ethernet, and CXL connectivity products.
- **Patented software-defined platform approach**: Differentiates via a platform that combines silicon hardware with embedded COSMOS software, enabling flexibility, observability, and predictive analytics.
- **Deep hyperscaler relationships**: Trusted partner to the world’s largest cloud providers, with proven interoperability validated in their own Cloud-Scale Interop Lab.
- **Broad product portfolio**: Covers PCIe retimers, Ethernet cable modules, CXL memory controllers, and fabric switches—addressing the full spectrum of AI connectivity bottlenecks.
- **Strong IP and engineering talent**: 443 employees in technical roles; talent sourced from Intel (65), Marvell (37), Texas Instruments (40), AMD (22), and NVIDIA.

## Strategic Focus
- **Scaling AI infrastructure**: Expanding product portfolio and global footprint (12 countries) to meet surging demand for rack-scale AI.
- **Open standards leadership**: All products are grounded in open standards (PCIe, CXL, Ethernet), ensuring interoperability and broad adoption.
- **Taiwan expansion**: Growing engineering presence and Interop Lab in Taiwan to strengthen integration with leading AI platform providers and system manufacturers.
- **Continued innovation**: Shipping the new 320-lane Scorpio X-Series Fabric Switch and expanding the COSMOS software suite for fleet-level management and optimization.

## Why Work Here
- **Culture**: Described as collaborative, ownership-driven, and focused on solving complex problems together. The company emphasizes diversity and inclusion as drivers of creativity and innovation.
- **Growth**: Astera Labs supports non-linear career growth—employees can deepen expertise (“scale up”) or broaden into new areas (“scale out”). 92% YoY headcount growth signals rapid expansion and opportunity.
- **Remote/Hybrid**: Not explicitly stated, but global operations across 12 countries (including India, Canada, Israel, Taiwan, Vietnam) suggest a flexible, distributed work model.
- **Benefits**: Competitive medical, dental, and vision plans; flexible time off; family planning and parental leave; 401K and retirement plans.
- **Engineering culture**: Strong focus on cutting-edge semiconductor and AI infrastructure technology. High concentration of senior (24%) and specialist (19%) talent. Active internship and new graduate programs.
- **Employee ratings**: 4.5/5.0 on LinkedIn (124 reviews), with high marks for compensation (4.6), culture (4.4), and career development (4.4).

## Sources
1. [Astera Labs Careers Page](https://www.asteralabs.com/careers/)
2. [Astera Labs Official Website](https://www.asteralabs.com/)
3. [Astera Labs LinkedIn](https://www.linkedin.com/company/astera-labs)
4. [Astera Labs Products Page](https://www.asteralabs.com/products/)
5. [Astera Labs S-1 Filing (SEC)](https://ir.asteralabs.com/static-files/7103a4cb-aa6b-4f11-a4b0-f179cd4c5bee)

## Other roles at Astera Labs

- [Template Job](https://feeny.ai/job/template-job-astera-labs-san-jose-california-hsrq2w5dnj4b) — San Jose California, United States
- [Principal Signal and Power Integrity Engineer](https://feeny.ai/job/principal-signal-and-power-integrity-engineer-astera-labs-shanghai-z3528r4p4kz5) — Shanghai, China
- [Principal Logic Design Engineer - UALink IP/Subsystem](https://feeny.ai/job/principal-logic-design-engineer-ualink-ip-subsystem-astera-labs-bengaluru-9shc23w9csza) — Bengaluru, India
- [Lead Logic Design - PCIE IP/Subsystem Engineer](https://feeny.ai/job/lead-logic-design-pcie-ip-subsystem-engineer-astera-labs-bengaluru-kwd80z6s6yng) — Bengaluru, India
- [Senior System Validation Engineer](https://feeny.ai/job/senior-system-validation-engineer-astera-labs-tel-aviv-yafo-7grrjpfc0rdd) — Tel Aviv-Yafo, Israel
- [Digital Design Manager](https://feeny.ai/job/digital-design-manager-astera-labs-toronto-crzqy4ghxbsq) — Toronto, Canada
- [Tech Lead, STA](https://feeny.ai/job/tech-lead-sta-astera-labs-hyderabad-b4sgrwnz1ybc) — Hyderabad, India
- [Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet](https://feeny.ai/job/principal-senior-principal-design-verification-engineer-cxl-pcie-ethernet-yzpz44j7h93t) — San Jose California, United States
- [Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet](https://feeny.ai/job/principal-senior-principal-design-verification-engineer-cxl-pcie-ethernet-0jtpt6yr55yd) — Taipei, Taiwan
- [Principal/ Sr Principal Digital Design Engineer](https://feeny.ai/job/principal-sr-principal-digital-design-engineer-astera-labs-taipei-dda1w0n4a6jr) — Taipei, Taiwan