---
title: 'Member of Technical Staff - Applied AI at Architect Labs'
canonical: 'https://feeny.ai/job/member-of-technical-staff-applied-ai-architect-labs-palo-alto-fn81mfsywneh'
type: 'job'
last_seen: '2026-09-09'
---

# Member of Technical Staff - Applied AI at Architect Labs

- **Company:** Architect Labs
- **Location:** Palo Alto, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-04-23
- **Last confirmed live:** 2026-09-09
- **Apply:** https://jobs.ashbyhq.com/architect/b2b1fc26-dc36-4309-921a-ba1780bdc992

## Job description

## ABOUT ARCHITECT

Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new era of domain-specific chips that unlock capabilities impossible with current hardware paradigms. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel.

## What You'll Do

As a Founding Member of the Technical Staff (Applied AI) at Architect, you'll sit at the intersection of chip design and frontier AI — translating deep hardware engineering expertise into agentic systems that can reason about, generate, and verify real silicon.

- Design and build AI agents that tackle core chip-design tasks, grounding model behavior in how real hardware engineers actually work.
- Own end-to-end agent workflows: scaffolding, tool use, evaluation harnesses, and the domain-specific infrastructure that makes agents useful on actual design problems.
- Serve as the hardware conscience of the model — curating high-quality data, defining evaluation criteria, and encoding the engineering judgment that separates plausible outputs from correct ones.
- Partner closely with the ML research, post-training, and infra teams to turn hardware domain expertise into reward signals, benchmarks, and training signal.
- Move fast in a 0→1 environment: prototype, dogfood, break things, iterate. Translate ambiguous chip-design challenges into concrete agent capabilities that ship.

## What We'd Like to See

Qualifications & Skills:

- Degree: MS or PhD in Electrical Engineering, Computer Engineering, EECS, or a closely related field.
- Hardware Background: Strong industry or research experience as an RTL design or Design Verification engineer, with a solid understanding of the modern chip design flow end to end.
- Software Engineering: Excellent software engineering fundamentals — comfortable writing clean, production-grade Python or typescript, building tooling, and working in modern engineering environments. This is a non-negotiable bar.
- Builder Mindset: Demonstrated ability to own ambiguous problems end to end, prototype quickly, and productionize what works. Pragmatic, not precious.
- Curiosity for AI: Genuine excitement about applying frontier AI to hardware. No prior applied-AI or ML research background is required — we'll meet you where you are.

Bonus:

- Prior experience on AI-for-chip-design or AI4EDA efforts at Google, NVIDIA, or at chip / EDA companies.
- Experience building, using, or evaluating LLM-based tooling for engineering workflows.
- Publications or open-source contributions at the intersection of ML and EDA (DAC, ICCAD, DVCon, MLCAD, NeurIPS, ICLR, ICML).
- Experience as an early engineer at a deeptech or AI startup.

## What We Offer

- Competitive salary and meaningful equity stake
- Fast-paced startup with autonomy and visible impact
- Cutting-edge AI-driven chip design challenges

## About Architect Labs

## Company Overview
- **One-liner**: Architect Labs builds an AI system that explores, designs, and provably verifies custom chips for the world's most demanding AI workloads.
- **Entity Type**: Private (Seed stage – $24M raised)
- **Headquarters**: United States (specific city not publicly available)
- **Founded**: Not publicly available
- **Founders**: Ebrahim Hussain & Aaditya Subedi

## Core Business
- **Primary industry**: Semiconductor / AI chip design
- **Target customers**: B2B, Enterprise (companies needing custom silicon for frontier AI models)
- **Mission**: "Frontier AI for Silicon" – to enable custom chip co-design by rethinking the entire design process from first principles, accelerating development cycles and allowing organizations to own their hardware.

## Products & Services
- **AI-Driven Chip Co-Design System**: A self-improving AI platform that explores, designs, and formally verifies chip architectures. It co-optimizes compilers, system software, runtimes, and models, collapsing the distance between model evolution and silicon deployment. Type: AI platform / service.

## Market Standing
- **Valuation**: Not disclosed
- **Key Metric**: Total Funding – $24M seed round (June 2026)
- **Notable Investors/Partners**: Kindred Ventures (lead), TQ Ventures (lead), Race Capital, Together Fund, plus angel investors Jeff Dean, Srinivas Narayanan, Lukasz Kaiser, Aravind Srinivas, Kunle Olokotun, Trevor Blackwell, Dr. Alex Wissner-Gross, and executives from NVIDIA, Google, OpenAI, Perplexity.
- **Growth Signals**: 
  - Raised $24M seed in June 2026 from top-tier investors.
  - Assembled an elite team of researchers and engineers from Anthropic, xAI, Google DeepMind, Meta, Intel, and Samsung.
  - Founders have backgrounds at Apple’s silicon teams and Tesla’s AI5 chip program; collectively the team has taped out 80+ production chips and managed multi-billion-dollar product lines.

## Competitive Advantages
- **First-principles approach**: Not adapting AI to legacy chip workflows but rebuilding the entire chip design process from scratch.
- **Provable verification**: AI system includes formal verification, reducing risk and iteration in chip design.
- **Convergent expertise**: Rare combination of frontier AI research and deep silicon design experience within the same team.
- **Self-improving system**: The platform learns from each design cycle, creating a flywheel of faster, better designs.

## Strategic Focus
- **Democratize custom chip co-design**: Make specialized silicon accessible beyond a handful of incumbents.
- **Shorten chip development cycles**: Move from multi-year cycles to software-like velocity.
- **Unified design space**: Enable synchronous optimization of models, compilers, runtimes, and hardware.

## Why Work Here
- **Frontier work**: Tackle one of the most ambitious problems in modern technology – AI-driven chip design.
- **Small, exceptional team**: Emphasis on ownership ("Surface Area"), relentless execution, and long-term craft.
- **Culture**: Values include depth, intellectual rigor, and rapid prototyping. Team members come from top AI and semiconductor labs.
- **Location/Policy**: Not explicitly stated; likely US-based with some flexibility. The careers page highlights a fully in-person culture for deep collaboration (inferred from "small team" and "end-to-end ownership"). 
- **Perks**: Not detailed, but the work involves cutting-edge research and infrastructure.

## Sources
1. [architectlabs.com](https://architectlabs.com/)
2. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/architect)
3. [linkedin.com](https://www.linkedin.com/company/architectlab)
4. [kindredventures.com](https://kindredventures.com/announcement/architect-labs-democratizing-custom-chip-co-design/)

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