--- title: 'Member of Technical Staff - Design Verification at Architect Labs' canonical: 'https://feeny.ai/job/member-of-technical-staff-design-verification-architect-labs-bengaluru-jf0s78hhyqrm' type: 'job' last_seen: '2026-09-09' --- # Member of Technical Staff - Design Verification at Architect Labs - **Company:** Architect Labs - **Location:** Bengaluru, India - **Employment:** full-time - **Work type:** onsite - **Posted:** 2026-07-22 - **Last confirmed live:** 2026-09-09 - **Apply:** https://jobs.ashbyhq.com/architect/a4fff40f-3b58-4642-8e51-7bdc6edb69f9 ## Job description ## ABOUT ARCHITECT Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new era of domain-specific chips that unlock capabilities impossible with current hardware paradigms. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel. ## WHAT YOU'LL DO As a Founding Member of the Technical Staff on the Design Verification team at Architect, you'll own the verification strategy behind AI-generated designs taping out on leading foundries. You'll work at the intersection of rigorous hardware verification and AI-driven design automation. - Review AI-driven test plan, and validation strategy for internal and external SoC projects. - Provide domain-specific expertise to our AI/ML teams, including architectural and microarchitectural checks, validation modularity, checkers, coverage models, and interface protocols — helping encode DV best practices into our AI-driven flows. - Independently define, drive, and coordinate validation, verification, and integration flows across multiple IPs, including checkpoints and collateral handoffs. - Collaborate with architecture, design, and AI/ML leads to generate simulation- and emulation-ready collateral that scales across projects. - Track emerging trends in semiconductor verification and AI-driven design automation to keep our methodology cutting-edge in quality, scalability, and throughput. ## WHAT WE'D LIKE TO SEE Qualifications & Skills: - Degree: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field. - Tapeout Experience: 5+ years (10+ preferred) working on advanced-node tapeouts at top chip companies or fast-moving silicon startups. End-to-end silicon delivery is a strong plus. - Verification Expertise: Deep expertise in verification/validation, emulation, and architectural and system-level verification of industry-standard IPs. Proven track record defining microarchitectural checkers and monitors, modeling IP and SoC validation platforms, and developing modular, reusable validation collateral. - Coding: Strong skills in SystemVerilog, UVM, and C/C++ for test environments. Python strongly preferred. - Subsystem Depth: Hands-on verification experience in at least one of the following areas: - ARM/AMBA protocols (APB, AHB, AXI, and ideally ACE for coherent CPU interfaces) - CPU subsystems — boot, interrupts, debug, coherency - Memory controllers and PHY — LPDDR/DDR interfaces, controller-level verification - On-chip interconnect / NoC — routing, arbitration, QoS, bandwidth - NPU / ML accelerator cores — datapath, scratchpad memory, DMA engines - Security IPs and/or working with secure enclaves - Methodology: Hands-on experience with simulation and emulation flows and methodologies. Experience mapping IP and SoC designs to FPGA prototypes for fast functional verification. - Execution: Excellent problem-solving, collaboration, and communication skills with strong attention to detail. Ability to work independently and drive cross-functional alignment. - Leadership: Ability and desire to lead the DV function over time as the team scales. Bonus: - SoC-level DV experience — bringing up full systems with memory controller + PHY + CPU connectivity, validating top-level integration. - Deep experience with AMBA protocols, specifically ACE for coherent CPU-memory access. - FPGA prototyping experience (ideally Xilinx Vivado/Vitis). - Verification experience spanning multiple of: interconnects, CPU subsystems, ARM AMBA, memory controllers, NPUs. - Tapeout experience at frontier AI chip startups (MatX, Groq, Cerebras, d-Matrix, etc.) or tier-1 silicon companies (Apple, NVIDIA, Google, Qualcomm, Broadcom, AMD). ## WHAT WE OFFER - Competitive salary and meaningful equity stake - Fast-paced startup with autonomy and visible impact - Cutting-edge challenges at the intersection of AI and silicon design ## About Architect Labs ## Company Overview - **One-liner**: Architect Labs builds an AI system that explores, designs, and provably verifies custom chips for the world's most demanding AI workloads. - **Entity Type**: Private (Seed stage – $24M raised) - **Headquarters**: United States (specific city not publicly available) - **Founded**: Not publicly available - **Founders**: Ebrahim Hussain & Aaditya Subedi ## Core Business - **Primary industry**: Semiconductor / AI chip design - **Target customers**: B2B, Enterprise (companies needing custom silicon for frontier AI models) - **Mission**: "Frontier AI for Silicon" – to enable custom chip co-design by rethinking the entire design process from first principles, accelerating development cycles and allowing organizations to own their hardware. ## Products & Services - **AI-Driven Chip Co-Design System**: A self-improving AI platform that explores, designs, and formally verifies chip architectures. It co-optimizes compilers, system software, runtimes, and models, collapsing the distance between model evolution and silicon deployment. Type: AI platform / service. ## Market Standing - **Valuation**: Not disclosed - **Key Metric**: Total Funding – $24M seed round (June 2026) - **Notable Investors/Partners**: Kindred Ventures (lead), TQ Ventures (lead), Race Capital, Together Fund, plus angel investors Jeff Dean, Srinivas Narayanan, Lukasz Kaiser, Aravind Srinivas, Kunle Olokotun, Trevor Blackwell, Dr. Alex Wissner-Gross, and executives from NVIDIA, Google, OpenAI, Perplexity. - **Growth Signals**: - Raised $24M seed in June 2026 from top-tier investors. - Assembled an elite team of researchers and engineers from Anthropic, xAI, Google DeepMind, Meta, Intel, and Samsung. - Founders have backgrounds at Apple’s silicon teams and Tesla’s AI5 chip program; collectively the team has taped out 80+ production chips and managed multi-billion-dollar product lines. ## Competitive Advantages - **First-principles approach**: Not adapting AI to legacy chip workflows but rebuilding the entire chip design process from scratch. - **Provable verification**: AI system includes formal verification, reducing risk and iteration in chip design. - **Convergent expertise**: Rare combination of frontier AI research and deep silicon design experience within the same team. - **Self-improving system**: The platform learns from each design cycle, creating a flywheel of faster, better designs. ## Strategic Focus - **Democratize custom chip co-design**: Make specialized silicon accessible beyond a handful of incumbents. - **Shorten chip development cycles**: Move from multi-year cycles to software-like velocity. - **Unified design space**: Enable synchronous optimization of models, compilers, runtimes, and hardware. ## Why Work Here - **Frontier work**: Tackle one of the most ambitious problems in modern technology – AI-driven chip design. - **Small, exceptional team**: Emphasis on ownership ("Surface Area"), relentless execution, and long-term craft. - **Culture**: Values include depth, intellectual rigor, and rapid prototyping. Team members come from top AI and semiconductor labs. - **Location/Policy**: Not explicitly stated; likely US-based with some flexibility. The careers page highlights a fully in-person culture for deep collaboration (inferred from "small team" and "end-to-end ownership"). - **Perks**: Not detailed, but the work involves cutting-edge research and infrastructure. ## Sources 1. [architectlabs.com](https://architectlabs.com/) 2. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/architect) 3. [linkedin.com](https://www.linkedin.com/company/architectlab) 4. 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