---
title: 'Member of Technical Staff, GPU Kernels at San Francisco Tensor Company'
canonical: 'https://feeny.ai/job/member-of-technical-staff-gpu-kernels-san-francisco-tensor-company-san-francisco-xckfx3rpw5vm'
type: 'job'
last_seen: '2026-09-13'
---

# Member of Technical Staff, GPU Kernels at San Francisco Tensor Company

- **Company:** San Francisco Tensor Company
- **Location:** San Francisco, CA
- **Compensation:** $285k–$315k
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-08-29
- **Last confirmed live:** 2026-09-13
- **Apply:** https://jobs.ashbyhq.com/sf-tensor/2238bd4b-3fa6-44b7-bdac-e1e04ae2fc78

## Job description

At SF Tensor, we're building the future of high-performance compute We firmly believe that the future of AI depends on the unglamorous: rethinking and rebuilding the stack, all the way down. From the hardware underneath it to the compiler targeting it and the cloud running it. Right now those three things fight each other and that friction shows up as a tax on every researcher trying to build something ambitious. We're here to axe that tax and make compute faster, cheaper and more available. When we succeed, compute will be portable enough that "which cloud, which chip" stop being something you worry about. To achieve this, we are building our Kernel Optimizer, which takes code and finds its fastest possible form for whatever vendor and cluster topology you point it at, automatically, as well as the Model Foundry which manages the runs, makes research easier and moves workloads across clouds and chips as prices and availability ship, instead of leaving you locked into whatever vendor you signed with first. We're backed by Susa Ventures, Y Combinator, along with some great funds and angels including Max Mullen and Paul Graham, as well as founders and executives at Neuralink, Notion and AMD. We're looking for researchers, engineers and organizations who agree with the basic premise: you don't get the next leap in AI without a leap in compute first.

## About the Role

We build the fastest GPU compiler in the world. Most compilers have to preserve correctness at every transform, constraining how far they can search, while we prove correctness at the end instead, allowing us to search a far wider space, with agents, with RL, with anything that works and still guarantee the result. It's why we hold #1 on NVIDIA's own kernel benchmark across hundreds of production kernels. We're hiring a Member of Technical Staff for GPU Kernel Engineering to establish and push the envelope on what the hardware can actually do before any search ever runs. To this extent, you'll write and hand-optimize kernels that execute during pre-training, post-training and inference, across NVIDIA, AMD, TPU and Trainium. You'll then take those learnings and convert them into structures the compiler can search: instruction sequences, scheduling strategies, cost signals, to ensure that the ceiling you worked for by hand can become the floor for the search finding kernels everywhere else. You'll have access to better tooling than anywhere else because we own the stack all the way down to the ISA, allowing us to create kernels that others can't even express. For example, our custom LLVM backend emits cubins directly, without a PTX handoff or ptxas doing our scheduling, letting us write kernels that have no expression in CUDA at all. Our team understands the hardware better than anyone else, to this extent we've built a bit-exact software model of Blackwell's [tcgen05](https://github.com/sf-tensor/tcgen05). You'll be writing kernels that ship immediately on runs such as pre-training AlphaFold v3 at 3.4× the throughput, post-training robotics models on Trainium or running our custom RL rollout engine on TPU at multi-100B parameter scale.

## What You'll Do

- You'll write and hand-optimize kernels for real workloads to find the ceiling before the search goes looking for it
- You'll profile at the microarchitectural level: SM and CU utilization, warp stalls, memory bank conflicts, register pressure, instruction throughput, occupancy tradeoffs
- You'll debug down to the clock behavior, thermal throttling and driver paths where the docs are often missing or just wrong
- You'll turn hard-won knowledge into a machine-searchable structure the compiler can explore on it's own
- You'll work below PTX at the ISA-level, reasoning about SASS and cubins to emit schedules PTX has no way to express
- You'll build the performance models, microbenchmarks and tooling that lets us predict kernel behavior
- You'll work alongside the formal correctness team, so that aggressive, unintuitive kernels ship with a formal proof attached

Expect roughly two-thirds of your time on kernels and one-third on turning what you learned into the compiler search space.

## What We're Looking For

- Someone with a track record of hand-writing kernels that match or beat vendor libraries
- Someone comfortable reading PTX, SASS, GCN/CDNA ISA or equivalent machine-level assembly
- Someone fluent with low-level profiling tools: Nsight Compute, Nsight Systems, rocprof, omniperf or their equivalent
- Someone with solid systems programming skills in C++ and CUDA or ROCm/HIP with a working understanding of how high-level ML operations map onto the hardware, including where the framework layers get in the way

## Nice to Have

- Someone who's worked on compiler backends (MLIR, LLVM, codegen, instruction selection, scheduling)
- Someone who's done research in the areas of superoptimization, program synthesis, formal verification or search-based compilation
- Someone who's worked with silicon beyond NVIDIA (AMD MI-series, TPU, Trainium) or mobile edge GPUs (Metal, Mali, Aderno)
- Someone who's worked on distributed AI training at depth
- Someone with experience in high-speed interconnects (NVLink, NVSwitch, InfiniBand, RoCE)
- Someone with an HPC background: large-scale scientific computing, MPI, supercomputing
- Someone who's worked in driver development or has a background in EE, computer architecture or hardware design

## Why Join Us

This role is for someone who wants to know why things are fast or slow on the actual silicon and is tired of watching that knowledge die undocumented in their own head the moment they move on to the next thing. The compiler takes what you found and runs the same search across every workload we touch, on every vendor's hardware, meaning every optimization compounds across thousands of kernels going forward. We're a small team operating at frontier scale. We pre-trained foundation models on 4,000 AMD GPUs as a team of three, designed and brought up GB300 NVL72 clusters and designed a TOP500 supercomputer. We believe that hard problems get solved in person and most of our work happens at our office in San Francisco. We offer relocation assistance and, where possible, we'd like you here as often as possible. The base salary range for this full-time position is $285,000-$315,000, plus meaningful equity and benefits.

## About San Francisco Tensor Company

## Company Overview
- **One-liner**: San Francisco Tensor Company (SF Tensor) builds an integrated stack of a programming language (Emma), an automatic kernel optimizer, and a cross-cloud compute platform (Tensor Cloud) to make AI and HPC workloads faster, cheaper, and hardware-portable.
- **Entity Type**: Private (Startup, Y Combinator Fall 2025 batch)
- **Headquarters**: San Francisco, California, USA
- **Founded**: 2025
- **Founders**: Ben Koska (CEO), Tom Koska, Luk Koska

## Core Business
- **Primary industry/industries**: AI Infrastructure, High-Performance Computing (HPC), Compiler & Kernel Optimization, Cloud Compute
- **Target customers**: AI research labs, AI startups, and enterprises training or running large-scale machine learning models (B2B).
- **Mission or purpose statement**: To reinvent how the world computes by making computation faster, cheaper, and more portable across every platform, thereby breaking the hardware vendor lock-in (e.g., NVIDIA's CUDA moat) and allowing researchers to focus on advancing models rather than managing infrastructure.

## Products & Services
- **[Emma Language]**: A new programming language designed to abstract away the quirks of individual hardware platforms (GPUs, TPUs, etc.) while delivering performance equivalent to hand-tuned kernels. Allows code to be written once and run on any hardware without rewriting.
- **[Kernel Optimizer]**: An automatic optimization engine that transforms training kernels into their mathematically fastest forms by simulating memory, cache, and hardware topology. It often exceeds the performance of hand-tuned human code. Available as a service.
- **[Tensor Cloud]**: A managed, cross-cloud compute platform that automatically finds the cheapest hardware (GPUs) across all major providers. It orchestrates training jobs, handles spot instance preemption, and manages infrastructure complexity for teams running from 1 to 10,000 GPUs. Cuts compute costs by up to 80%.

## Market Standing
- **Valuation/Market Cap**: Not publicly available (early-stage startup).
- **Key Metric**: Total Funding – Backed by Y Combinator (Fall 2025 batch). Specific funding amount not disclosed. Revenue is not publicly available.
- **Notable Investors/Partners**: Y Combinator (Primary Partner: Harj Taggar).
- **Growth Signals**: The company was founded in 2025 and is already live with Tensor Cloud, a Kernel Optimizer, and the Emma language preview. It has a team of 6 people and is actively hiring for multiple founding-level engineering roles, indicating rapid early-stage scaling.

## Competitive Advantages
- **Integrated Full Stack**: By combining a purpose-built language (Emma), a hardware-aware kernel optimizer, and a cross-cloud orchestration platform, they offer a unified solution that competitors typically only address piecemeal.
- **Hardware Agnosticism**: Their core mission is to break the CUDA moat, making it easy for AI teams to run on AMD, Google, or Amazon hardware without performance loss, thereby reducing costs and dependency on NVIDIA.
- **Automatic Optimization**: Their kernel optimizer claims to beat hand-tuned implementations by using algorithmic reformulation based on micro-benchmarking of hardware topology, a deep technical moat.
- **Founding Team**: Founders with deep technical backgrounds (Ben Koska finished a BSc in CS at age 16) and a clear, ambitious vision.

## Strategic Focus
- **Product Development**: Continuing to build out the Emma language, the Kernel Optimizer, and Tensor Cloud into a seamless, production-ready platform.
- **Market Adoption**: Onboarding early design partners and AI labs to validate the stack and build a user base.
- **Hiring**: Aggressively hiring founding engineers (GPU Kernel, Compiler, Research, Product) to scale the team and accelerate development.
- **Breaking Vendor Lock-in**: A core strategic goal is to provide a viable alternative to NVIDIA's CUDA ecosystem, enabling customers to leverage cheaper, non-NVIDIA hardware.

## Why Work Here
- **Mission-Driven**: Opportunity to solve one of the hardest and most impactful problems in AI: the compute bottleneck and infrastructure complexity.
- **Technical Depth**: The work involves pushing hardware to its limits, designing new programming languages, and writing cutting-edge compilers and kernel code. The culture values deep technical engagement.
- **Founding Team Impact**: As a very early-stage company (6 people), new hires will be founding engineers with significant ownership, equity (1% - 2% range for some roles), and influence over the product and culture.
- **Compensation**: Offers competitive salary in the 90th percentile+ (e.g., $225k-$315k base for some roles), plus meaningful equity.
- **Benefits**: Premium health, dental, and vision insurance for employee and family; unlimited PTO; generous parental leave; 401K with salary matching; team offsites and retreats.
- **Work Environment**: Described as a team of builders, mathematicians, and systems thinkers. They emphasize moving fast without cutting corners. The hiring process is rigorous and transparent.
- **Location**: Based in San Francisco, CA. Roles are listed as on-site.

## Sources
1. [sf-tensor.com](https://sf-tensor.com/)
2. [sf-tensor.com/careers](https://sf-tensor.com/careers)
3. [ycombinator.com](https://www.ycombinator.com/companies/sf-tensor)
4. [sf-tensor.com/news](https://sf-tensor.com/news/introducing-sf-tensor)
5. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/sf-tensor)

## Other roles at San Francisco Tensor Company

- [Member of Technical Staff, Post-Training & Applied Research](https://feeny.ai/job/member-of-technical-staff-post-training-applied-research-san-francisco-tensor-rj1qrpm2j557) — San Francisco, CA
- [Member of Technical Staff, AI-Driven Compilation](https://feeny.ai/job/member-of-technical-staff-ai-driven-compilation-san-francisco-tensor-company-q9veb1f860mf) — San Francisco, CA
- [Member of Technical Staff, Product Engineering](https://feeny.ai/job/member-of-technical-staff-product-engineering-san-francisco-tensor-company-san-41h1c6445kr8) — San Francisco, CA
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