---
title: 'Member of Technical Staff - Microarchitect / RTL Design at Architect Labs'
canonical: 'https://feeny.ai/job/member-of-technical-staff-microarchitect-rtl-design-architect-labs-palo-alto-1afm42nm1f35'
type: 'job'
last_seen: '2026-09-09'
---

# Member of Technical Staff - Microarchitect / RTL Design at Architect Labs

- **Company:** Architect Labs
- **Location:** Palo Alto, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-04-16
- **Last confirmed live:** 2026-09-09
- **Apply:** https://jobs.ashbyhq.com/architect/c33d76c5-599d-4655-bb64-a59e281fc532

## Job description

## ABOUT ARCHITECT

Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new era of domain-specific chips that unlock capabilities impossible with current hardware paradigms. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel.

## WHAT YOU'LL DO

As a Founding Member of the Technical Staff on the RTL Design team at Architect, you'll own the AI-driven microarchitecture and RTL design of mission-critical SoC blocks and sub-systems (SS) going into production silicon. You will be expected to define, drive, and revise the block-level micro-arch specification for one of the fundamental HW accelerator blocks.

As such, you fit our current opportunities if you have hands-on design and block-owner experience in any of the following ASIC components: on-chip memory SS, on-chip interconnect SS (NoCs, DMAs, etc.) with custom or standard protocols (AXI, etc.), IO and peripherals integration (PCIe, DDR, CXL, etc.), CPU/Host/controllers, Security, Compression, Debug/DFT (BIST, MBIST, etc.), and specialized accelerators such as ML/AI accelerators (NPUs, TPUs, etc.), SIMD vector engines, DSPs, GPUs, graphics/audio pipelines.

As a lab, we are investing in building a world-class HW design team, so if you think you have a particular experience/background that is not listed here, please still reach out to us!

- Own AI-driven RTL design flow end-to-end (at the frontend): through code generation to incorporating feedback from lint, CDC, synthesis, and timing closure stages for closing the design loop.
- Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs, and feed area/timing/power realities back into the architecture and internal AI systems.
- Define and maintain interface specifications (e.g. AXI, AXI-Stream, or custom-built) for block- and SS-level integration.
- Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, regression flows, lint/CDC waivers, and integration collateral.
- Close collaboration with DV: Support DV bring-up with reference models, assertions, test-plans, and architectural documentation for verification closure.
- Close collaboration with SW and ML: Support and guide our SW and ML experts to revise and improve our in-house AI flow based on your own experience.
- Support FPGA prototyping on Xilinx for early functional validation.

## WHAT WE'D LIKE TO SEE

Qualifications & Skills:

- Degree: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
- Experience: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience, worked on specialized HW accelerators.
- SystemVerilog: Clear, synthesizable, lint-clean RTL with strong design habits such as parameterization, modularity, reuse and configurability.
- Block-Level Depth: Hands-on experience with block-specific compute datapaths and data movement; such as MAC arrays, vector units, accumulators, on-chip SRAM controllers and arbiters, DMA engines, scratchpad memory management, etc.
- SoC Methodology: Solid grasp of synthesis, timing constraints, clock domain crossings, reset strategies, AMBA protocols (AXI, AHB, APB), power management techniques, etc.
- Python: Strong skills for design automation, regression infrastructure, and tooling.
- PPA Ownership: Experience taking a block from RTL through synthesis and working with PD teams on timing/area/power closure.
- Leadership: Ability to lead RTL design efforts and grow into a team lead over time.

Bonus:

- Low-power design techniques: clock gating, power gating, multi-voltage domains, UPF.
- FPGA prototyping experience (ideally Xilinx Vivado/Vitis).
- Familiarity with SIMD/VLIW execution pipelines or instruction-driven datapath design.
- Experience writing SVA assertions and functional coverage for design-side verification.
- Prior IP building and delivery experience on your block-of-expertise, such as DMA controllers, memory subsystems, interconnects, or similar SoC infrastructure blocks.
- Domain-specific expertise: Track record on research and development on energy-efficient, high-performance HW accelerators on your block-of-expertise.

## WHAT WE OFFER

- Competitive salary and meaningful equity stake
- Fast-paced startup with autonomy and visible impact
- Cutting-edge challenges at the intersection of AI and silicon design

## About Architect Labs

## Company Overview
- **One-liner**: Architect Labs builds an AI system that explores, designs, and provably verifies custom chips for the world's most demanding AI workloads.
- **Entity Type**: Private (Seed stage – $24M raised)
- **Headquarters**: United States (specific city not publicly available)
- **Founded**: Not publicly available
- **Founders**: Ebrahim Hussain & Aaditya Subedi

## Core Business
- **Primary industry**: Semiconductor / AI chip design
- **Target customers**: B2B, Enterprise (companies needing custom silicon for frontier AI models)
- **Mission**: "Frontier AI for Silicon" – to enable custom chip co-design by rethinking the entire design process from first principles, accelerating development cycles and allowing organizations to own their hardware.

## Products & Services
- **AI-Driven Chip Co-Design System**: A self-improving AI platform that explores, designs, and formally verifies chip architectures. It co-optimizes compilers, system software, runtimes, and models, collapsing the distance between model evolution and silicon deployment. Type: AI platform / service.

## Market Standing
- **Valuation**: Not disclosed
- **Key Metric**: Total Funding – $24M seed round (June 2026)
- **Notable Investors/Partners**: Kindred Ventures (lead), TQ Ventures (lead), Race Capital, Together Fund, plus angel investors Jeff Dean, Srinivas Narayanan, Lukasz Kaiser, Aravind Srinivas, Kunle Olokotun, Trevor Blackwell, Dr. Alex Wissner-Gross, and executives from NVIDIA, Google, OpenAI, Perplexity.
- **Growth Signals**: 
  - Raised $24M seed in June 2026 from top-tier investors.
  - Assembled an elite team of researchers and engineers from Anthropic, xAI, Google DeepMind, Meta, Intel, and Samsung.
  - Founders have backgrounds at Apple’s silicon teams and Tesla’s AI5 chip program; collectively the team has taped out 80+ production chips and managed multi-billion-dollar product lines.

## Competitive Advantages
- **First-principles approach**: Not adapting AI to legacy chip workflows but rebuilding the entire chip design process from scratch.
- **Provable verification**: AI system includes formal verification, reducing risk and iteration in chip design.
- **Convergent expertise**: Rare combination of frontier AI research and deep silicon design experience within the same team.
- **Self-improving system**: The platform learns from each design cycle, creating a flywheel of faster, better designs.

## Strategic Focus
- **Democratize custom chip co-design**: Make specialized silicon accessible beyond a handful of incumbents.
- **Shorten chip development cycles**: Move from multi-year cycles to software-like velocity.
- **Unified design space**: Enable synchronous optimization of models, compilers, runtimes, and hardware.

## Why Work Here
- **Frontier work**: Tackle one of the most ambitious problems in modern technology – AI-driven chip design.
- **Small, exceptional team**: Emphasis on ownership ("Surface Area"), relentless execution, and long-term craft.
- **Culture**: Values include depth, intellectual rigor, and rapid prototyping. Team members come from top AI and semiconductor labs.
- **Location/Policy**: Not explicitly stated; likely US-based with some flexibility. The careers page highlights a fully in-person culture for deep collaboration (inferred from "small team" and "end-to-end ownership"). 
- **Perks**: Not detailed, but the work involves cutting-edge research and infrastructure.

## Sources
1. [architectlabs.com](https://architectlabs.com/)
2. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/architect)
3. [linkedin.com](https://www.linkedin.com/company/architectlab)
4. [kindredventures.com](https://kindredventures.com/announcement/architect-labs-democratizing-custom-chip-co-design/)

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