--- title: 'Member of Technical Staff - ML Research at Architect Labs' canonical: 'https://feeny.ai/job/member-of-technical-staff-ml-research-architect-labs-palo-alto-54806jz19wsf' type: 'job' last_seen: '2026-10-14' --- # Member of Technical Staff - ML Research at Architect Labs - **Company:** Architect Labs - **Location:** Palo Alto, CA - **Employment:** full-time - **Work type:** onsite - **Posted:** 2026-02-10 - **Last confirmed live:** 2026-10-14 - **Apply:** https://jobs.ashbyhq.com/architect/4d9a8c84-12ab-47e1-9b76-65e1a0dcada4 ## Job description ## About Architect Labs Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world. ## What You'll Do As a Member of the Technical Staff at Architect, you'll be at the forefront of training AI models for chip design, verification and exploration tasks. You will be doing fundamental research and applying that to industry-grade chips going into production at leading foundry technologies like TSMC. - Responsible for co-designing and implementing the Reinforcement Learning environments and algorithms, Reward Models trainings and reward signal experiments. - You will work at the intersection of cutting-edge research and production engineering for chip designs, implementing, scaling, and improving post-training techniques to enhance model capabilities and usability . - Design, build, and run robust, efficient pipelines for model fine-tuning and evaluation, ensuring that theoretical performance translates into production-ready implementations. - This is a hands-on, 0→1 role where you'll own the end-to-end RL workflow—from reward modeling and environment design to test-time optimization and scaling. - Collaborate with research teams to translate emerging techniques into production-ready implementations and debug complex issues in training pipelines and model behavior. ## What We'd Like to See Qualifications & Skills: - Degree: PhD in Computer Science, Computer Engineering, EECS, Mathematics, or a closely related field. Preferably, specialization in Machine Learning, Deep Learning, or Artificial Intelligence. Or BS/MS with a strong research engineering background. - RL & Post-Training Expertise: Deep expertise in reinforcement learning and post-training, with a proven track record of taking models from research to real-world deployment. - Model Training: Strong industry or research background building end-to-end ML pipelines. Experience RL and fine-tuning LLMs and code models for reasoning, tool use, and structured coding tasks. - Systems Engineering: Strong software engineering skills with experience building complex ML systems. Comfortable working with large-scale distributed systems, high-performance computing, and distributed training frameworks (e.g., PyTorch, CUDA, QLoRA, ZeRO). - Engineering Rigor: Adept at analyzing and debugging model training processes. Capable of balancing research exploration with engineering rigor and operational reliability. - Execution: Fast-moving builder who can prototype, benchmark, and productionize training pipelines with tight feedback loops. Bonus: - Worked on the post-training team at frontier labs like OpenAI, Anthropic, DeepMind, Mistral, MSL, Cohere, etc. - Foundation in Electrical/Computer Engineering, Computer Architecture, and chip-design or verification processes (not required, but a plus). - Publications in top ML (NeurIPS, ICLR, ICML) or EDA (DAC, ICCAD, DVCon) venues. - Experience as a Founding ML Engineer/Researcher or early hire at an AI deeptech startup. ## What We Offer - Competitive salary and meaningful equity stake - Fast-paced startup with autonomy and visible impact - Cutting-edge AI-driven chip design challenges ## About Architect Labs ## Company Overview - **One-liner**: Architect Labs builds an AI system that explores, designs, and provably verifies custom chips for the world's most demanding AI workloads. - **Entity Type**: Private (Seed stage – $24M raised) - **Headquarters**: United States (specific city not publicly available) - **Founded**: Not publicly available - **Founders**: Ebrahim Hussain & Aaditya Subedi ## Core Business - **Primary industry**: Semiconductor / AI chip design - **Target customers**: B2B, Enterprise (companies needing custom silicon for frontier AI models) - **Mission**: "Frontier AI for Silicon" – to enable custom chip co-design by rethinking the entire design process from first principles, accelerating development cycles and allowing organizations to own their hardware. ## Products & Services - **AI-Driven Chip Co-Design System**: A self-improving AI platform that explores, designs, and formally verifies chip architectures. It co-optimizes compilers, system software, runtimes, and models, collapsing the distance between model evolution and silicon deployment. Type: AI platform / service. ## Market Standing - **Valuation**: Not disclosed - **Key Metric**: Total Funding – $24M seed round (June 2026) - **Notable Investors/Partners**: Kindred Ventures (lead), TQ Ventures (lead), Race Capital, Together Fund, plus angel investors Jeff Dean, Srinivas Narayanan, Lukasz Kaiser, Aravind Srinivas, Kunle Olokotun, Trevor Blackwell, Dr. Alex Wissner-Gross, and executives from NVIDIA, Google, OpenAI, Perplexity. - **Growth Signals**: - Raised $24M seed in June 2026 from top-tier investors. - Assembled an elite team of researchers and engineers from Anthropic, xAI, Google DeepMind, Meta, Intel, and Samsung. - Founders have backgrounds at Apple’s silicon teams and Tesla’s AI5 chip program; collectively the team has taped out 80+ production chips and managed multi-billion-dollar product lines. ## Competitive Advantages - **First-principles approach**: Not adapting AI to legacy chip workflows but rebuilding the entire chip design process from scratch. - **Provable verification**: AI system includes formal verification, reducing risk and iteration in chip design. - **Convergent expertise**: Rare combination of frontier AI research and deep silicon design experience within the same team. - **Self-improving system**: The platform learns from each design cycle, creating a flywheel of faster, better designs. ## Strategic Focus - **Democratize custom chip co-design**: Make specialized silicon accessible beyond a handful of incumbents. - **Shorten chip development cycles**: Move from multi-year cycles to software-like velocity. - **Unified design space**: Enable synchronous optimization of models, compilers, runtimes, and hardware. ## Why Work Here - **Frontier work**: Tackle one of the most ambitious problems in modern technology – AI-driven chip design. - **Small, exceptional team**: Emphasis on ownership ("Surface Area"), relentless execution, and long-term craft. - **Culture**: Values include depth, intellectual rigor, and rapid prototyping. Team members come from top AI and semiconductor labs. - **Location/Policy**: Not explicitly stated; likely US-based with some flexibility. The careers page highlights a fully in-person culture for deep collaboration (inferred from "small team" and "end-to-end ownership"). - **Perks**: Not detailed, but the work involves cutting-edge research and infrastructure. ## Sources 1. [architectlabs.com](https://architectlabs.com/) 2. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/architect) 3. [linkedin.com](https://www.linkedin.com/company/architectlab) 4. [kindredventures.com](https://kindredventures.com/announcement/architect-labs-democratizing-custom-chip-co-design/) ## Other roles at Architect Labs - [Member of Technical Staff - Physical Design](https://feeny.ai/job/member-of-technical-staff-physical-design-architect-labs-palo-alto-w148jdht2ctd) — Palo Alto, CA - [Member of Technical Staff - Formal Verification](https://feeny.ai/job/member-of-technical-staff-formal-verification-architect-labs-palo-alto-1nmp3kygr0de) — Palo Alto, CA - [Microarchitect / RTL Design - Memory Subsystem](https://feeny.ai/job/microarchitect-rtl-design-memory-subsystem-architect-labs-palo-alto-y0j0qnyxfc2j) — Palo Alto, CA - [Microarchitect / RTL Design - Interconnect & Fabric](https://feeny.ai/job/microarchitect-rtl-design-interconnect-fabric-architect-labs-palo-alto-7eqe6bxeewnb) — Palo Alto, CA - [Member of Technical Staff - Microarchitectural Validation](https://feeny.ai/job/member-of-technical-staff-microarchitectural-validation-architect-labs-palo-alto-03kf2jzzyf0m) — Palo Alto, CA - [Member of Technical Staff - Microarchitectural Validation](https://feeny.ai/job/member-of-technical-staff-microarchitectural-validation-architect-labs-bengaluru-jf0s78hhyqrm) — Bengaluru, India - [Member of Technical Staff - Software](https://feeny.ai/job/member-of-technical-staff-software-architect-labs-palo-alto-nhxbtrya6akb) — Palo Alto, CA - [Member of Technical Staff - Formal Methods](https://feeny.ai/job/member-of-technical-staff-formal-methods-architect-labs-palo-alto-3np6mmsb8wz6) — Palo Alto, CA - [Member of Technical Staff - AI for Chip Design](https://feeny.ai/job/member-of-technical-staff-ai-for-chip-design-architect-labs-palo-alto-fn81mfsywneh) — Palo Alto, CA - [General Application](https://feeny.ai/job/general-application-architect-labs-palo-alto-7hmn44c5b1c7) — Palo Alto, CA