---
title: 'Member of Technical Staff - Physical Design at Architect Labs'
canonical: 'https://feeny.ai/job/member-of-technical-staff-physical-design-architect-labs-palo-alto-w148jdht2ctd'
type: 'job'
last_seen: '2026-09-16'
---

# Member of Technical Staff - Physical Design at Architect Labs

- **Company:** Architect Labs
- **Location:** Palo Alto, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-09-14
- **Last confirmed live:** 2026-09-16
- **Apply:** https://jobs.ashbyhq.com/architect/2e0d4877-52cd-4142-9413-9349545c0870

## Job description

## About Architect Labs

Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, OEMs and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.

## What You'll Do

As our first Physical Design engineer, you'll build the PD function from scratch and extend our AI system from spec-to-netlist to tapeout-ready GDS. You'll own the methodology and hands-on execution for physical implementation at 3nm, 2nm, and future leading-edge nodes.

- Build the methodology: Establish and qualify the complete netlist-to-GDS flow, including PDKs, libraries, tools, constraints, automation, and reproducible regression infrastructure.
- Own implementation: Personally drive block and full-chip floorplanning, power planning, placement, clock tree synthesis, routing, and ECOs to meet demanding PPA targets.
- Drive signoff: Define release criteria and close timing, signal integrity, EM/IR, DRC/LVS, and foundry-required physical checks through final GDS delivery.
- Work with AI researchers: Translate PD expertise into automated flows, structured tool feedback, and evaluations. Feed post-route results back into architecture, RTL, and our AI system.
- Lead technical partnerships: Resolve process, library, tool, and signoff challenges directly with foundries, EDA vendors, and IP providers.
- Build the team: Set technical standards, define the PD roadmap and hiring priorities, and mentor future hires while remaining hands-on.

## What We'd Like to See

Qualifications & Skills:

- Tapeout ownership: Multiple production tapeouts, with direct physical implementation and signoff responsibility at 3nm or 2nm and experience leading full-chip closure.
- Methodology development: A track record of building production PD methodology from scratch for advanced nodes, including PDK/library qualification, tool evaluation, and deployment across chip programs.
- Technical depth: Deep expertise in hierarchical implementation, multi-mode multi-corner timing analysis, variation, clocking, congestion, low-power design, extraction, and power integrity.
- EDA expertise: Recent hands-on mastery of Synopsys Fusion Compiler/ICC2 or Cadence Innovus, along with commercial timing, extraction, power integrity, and physical verification tools.
- Automation: Strong Tcl and Python skills, with experience building maintainable flow scripts, automated checks, regressions, and actionable PPA reporting.
- Technical leadership: Ability to independently establish the flow, debug difficult closure problems, and explain implementation trade-offs to hardware, software, and AI teams.

Bonus:

- Direct 2nm methodology bring-up and tapeout experience, including GAA/nanosheet implementation and evolving PDK or library qualification.
- Implementation of high-performance CPUs, GPUs, AI accelerators, or complex custom SoCs with demanding frequency and power targets.
- Experience with design-technology co-optimization, chiplets, multi-die integration, or backside power delivery where supported by the target process.
- Prior experience as a founding PD engineer or building methodology adopted across multiple teams and chip programs.

## What We Offer

Competitive compensation and meaningful equity, autonomy to establish the PD function, and the opportunity to shape AI-driven silicon design from implementation through tapeout.

## About Architect Labs

## Company Overview
- **One-liner**: Architect Labs builds an AI system that explores, designs, and provably verifies custom chips for the world's most demanding AI workloads.
- **Entity Type**: Private (Seed stage – $24M raised)
- **Headquarters**: United States (specific city not publicly available)
- **Founded**: Not publicly available
- **Founders**: Ebrahim Hussain & Aaditya Subedi

## Core Business
- **Primary industry**: Semiconductor / AI chip design
- **Target customers**: B2B, Enterprise (companies needing custom silicon for frontier AI models)
- **Mission**: "Frontier AI for Silicon" – to enable custom chip co-design by rethinking the entire design process from first principles, accelerating development cycles and allowing organizations to own their hardware.

## Products & Services
- **AI-Driven Chip Co-Design System**: A self-improving AI platform that explores, designs, and formally verifies chip architectures. It co-optimizes compilers, system software, runtimes, and models, collapsing the distance between model evolution and silicon deployment. Type: AI platform / service.

## Market Standing
- **Valuation**: Not disclosed
- **Key Metric**: Total Funding – $24M seed round (June 2026)
- **Notable Investors/Partners**: Kindred Ventures (lead), TQ Ventures (lead), Race Capital, Together Fund, plus angel investors Jeff Dean, Srinivas Narayanan, Lukasz Kaiser, Aravind Srinivas, Kunle Olokotun, Trevor Blackwell, Dr. Alex Wissner-Gross, and executives from NVIDIA, Google, OpenAI, Perplexity.
- **Growth Signals**: 
  - Raised $24M seed in June 2026 from top-tier investors.
  - Assembled an elite team of researchers and engineers from Anthropic, xAI, Google DeepMind, Meta, Intel, and Samsung.
  - Founders have backgrounds at Apple’s silicon teams and Tesla’s AI5 chip program; collectively the team has taped out 80+ production chips and managed multi-billion-dollar product lines.

## Competitive Advantages
- **First-principles approach**: Not adapting AI to legacy chip workflows but rebuilding the entire chip design process from scratch.
- **Provable verification**: AI system includes formal verification, reducing risk and iteration in chip design.
- **Convergent expertise**: Rare combination of frontier AI research and deep silicon design experience within the same team.
- **Self-improving system**: The platform learns from each design cycle, creating a flywheel of faster, better designs.

## Strategic Focus
- **Democratize custom chip co-design**: Make specialized silicon accessible beyond a handful of incumbents.
- **Shorten chip development cycles**: Move from multi-year cycles to software-like velocity.
- **Unified design space**: Enable synchronous optimization of models, compilers, runtimes, and hardware.

## Why Work Here
- **Frontier work**: Tackle one of the most ambitious problems in modern technology – AI-driven chip design.
- **Small, exceptional team**: Emphasis on ownership ("Surface Area"), relentless execution, and long-term craft.
- **Culture**: Values include depth, intellectual rigor, and rapid prototyping. Team members come from top AI and semiconductor labs.
- **Location/Policy**: Not explicitly stated; likely US-based with some flexibility. The careers page highlights a fully in-person culture for deep collaboration (inferred from "small team" and "end-to-end ownership"). 
- **Perks**: Not detailed, but the work involves cutting-edge research and infrastructure.

## Sources
1. [architectlabs.com](https://architectlabs.com/)
2. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/architect)
3. [linkedin.com](https://www.linkedin.com/company/architectlab)
4. [kindredventures.com](https://kindredventures.com/announcement/architect-labs-democratizing-custom-chip-co-design/)

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