---
title: 'Microarchitect / RTL Design - Memory Subsystem at Architect Labs'
canonical: 'https://feeny.ai/job/microarchitect-rtl-design-memory-subsystem-architect-labs-palo-alto-y0j0qnyxfc2j'
type: 'job'
last_seen: '2026-09-09'
---

# Microarchitect / RTL Design - Memory Subsystem at Architect Labs

- **Company:** Architect Labs
- **Location:** Palo Alto, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-08-12
- **Last confirmed live:** 2026-09-09
- **Apply:** https://jobs.ashbyhq.com/architect/cf660067-8872-445a-849b-cfc4d10bf1d1

## Job description

## ABOUT ARCHITECT

Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new era of domain-specific chips that unlock capabilities impossible with current hardware paradigms. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel.

## WHAT YOU’LL DO

As a Founding Member of the Technical Staff on the RTL Design team at Architect, you’ll own the AI-driven microarchitecture and RTL design of the memory subsystem going into production silicon. You will define, drive, and revise the block-level micro-architecture specification for memory controllers, memory hierarchy management, and memory-side accelerators — ensuring maximum bandwidth utilization, minimal latency, and efficient power delivery for compute-intensive ML workloads.

## CORE RESPONSIBILITIES

- Own the memory subsystem RTL end-to-end: from DDR/HBM controller design through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow.
- Design and implement memory controllers: including DDR5/LPDDR5X PHY-side controller logic, HBM3/HBM3E pseudo-channel controllers, command scheduling (open-page/close-page policies, bank-level parallelism), refresh management, and ECC/RAS engines.
- Architect the memory hierarchy: including multi-level cache controllers, scratchpad memory managers, coherency protocol engines (where applicable), prefetch engines, and bandwidth partitioning/QoS mechanisms to serve diverse traffic profiles from ML accelerator datapaths.
- Design memory-side accelerators: near-memory compute logic, scatter-gather DMA engines, address translation/remapping units, compression/decompression engines co-located with memory interfaces, and intelligent prefetchers tuned for ML access patterns.
- Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs (bandwidth vs. latency vs. area vs. power), and feed area/timing/power realities back into the architecture and internal AI systems.
- Define and maintain interface specifications: DDR PHY interfaces (DFI), HBM PHY interfaces, on-chip SRAM interfaces, AXI/ACE/CHI for memory-facing fabric ports, and custom interfaces for near-memory accelerator datapaths.
- Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, regression flows, lint/CDC waivers, and integration collateral for the memory subsystem.
- Close collaboration with DV: Support verification bring-up with memory timing models, protocol-compliant BFMs, SVA assertions for JEDEC protocol compliance, coverage plans targeting worst-case scheduling scenarios, and architectural documentation for verification closure.
- Close collaboration with SW and ML: Support and guide our SW and ML experts to revise and improve our in-house AI flow based on your memory subsystem domain expertise — particularly around workload-driven memory access pattern optimization.
- Support FPGA prototyping on Xilinx for early functional validation of memory controllers, including bring-up with DDR MIG IPs and HBM validation platforms.

## WHAT WE’D LIKE TO SEE

## REQUIRED QUALIFICATIONS

- Degree: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
- Experience: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience involving memory subsystems (DDR/LPDDR/HBM controllers, cache hierarchies, or memory-intensive SoC subsystems).
- Memory Interface Expertise: Deep familiarity with JEDEC memory standards — DDR5/LPDDR5X command/address protocols, timing parameters, training sequences, and/or HBM2E/HBM3 pseudo-channel architecture, stack addressing, and interleaving schemes.
- Memory Controller Design: Hands-on experience designing or owning memory controller blocks including command schedulers, bank state machines, refresh engines (per-bank, fine-granularity), read/write turnaround optimization, and PHY interface timing (DFI or proprietary).
- Memory Hierarchy Architecture: Experience with multi-level cache design (tag/data arrays, replacement policies, coherence protocols), scratchpad controllers, or unified memory architectures with partitioning and QoS.
- SystemVerilog: Clear, synthesizable, lint-clean RTL with strong design habits — parameterization for multi-standard support (DDR5/HBM3), modularity for channel/pseudo-channel instantiation, and configurability for different capacity/bandwidth targets.
- Block-Level Depth: Hands-on experience with SRAM controllers and arbiters, bank conflict resolution, address hashing/interleaving, ECC encode/decode engines, and high-bandwidth data movement between on-chip and off-chip memory.
- SoC Methodology: Solid grasp of synthesis, timing constraints, clock domain crossings (PHY-to-controller domain, multi-frequency memory interfaces), reset strategies, AMBA protocols (AXI, ACE, CHI), and power management for memory subsystems.
- Python: Strong skills for design automation, performance modeling, regression infrastructure, and tooling.
- PPA Ownership: Experience taking a memory controller or cache subsystem from RTL through synthesis and working with PD teams on timing/area/power closure — particularly for high-frequency controller logic and wide data buses.

## BONUS QUALIFICATIONS

- Experience with HBM integration: interposer-level considerations, PHY calibration, thermal management impacts on refresh.
- Familiarity with CXL memory pooling, Type 3 device controllers, or disaggregated memory architectures.
- Near-memory or processing-in-memory (PIM) design experience.
- Low-power design techniques: DVFS-aware memory scheduling, partial-array self-refresh, clock gating of idle channels, power gating of unused banks.
- FPGA prototyping experience (Xilinx Vivado/Vitis) with DDR MIG or HBM subsystem IP integration.
- SVA assertions for JEDEC protocol compliance (command sequencing, timing parameter checking, training state machines).
- Prior IP building and delivery experience for DDR/LPDDR controllers, HBM controllers, or cache subsystem IPs.
- Performance modeling: experience building or using cycle-accurate memory system simulators (e.g., DRAMSim, Ramulator) to validate microarchitectural decisions.
- Domain-specific research contributions: publications or patents in memory systems, memory scheduling algorithms, or memory-centric compute architectures for ML workloads.

## WHY ARCHITECT

You’ll join a founding team building the future of chip design at the intersection of AI and silicon. Your memory subsystem expertise will directly shape production ASICs — enabling the bandwidth and efficiency that ML workloads demand — and influence how AI transforms hardware development from spec to tapeout.

## About Architect Labs

## Company Overview
- **One-liner**: Architect Labs builds an AI system that explores, designs, and provably verifies custom chips for the world's most demanding AI workloads.
- **Entity Type**: Private (Seed stage – $24M raised)
- **Headquarters**: United States (specific city not publicly available)
- **Founded**: Not publicly available
- **Founders**: Ebrahim Hussain & Aaditya Subedi

## Core Business
- **Primary industry**: Semiconductor / AI chip design
- **Target customers**: B2B, Enterprise (companies needing custom silicon for frontier AI models)
- **Mission**: "Frontier AI for Silicon" – to enable custom chip co-design by rethinking the entire design process from first principles, accelerating development cycles and allowing organizations to own their hardware.

## Products & Services
- **AI-Driven Chip Co-Design System**: A self-improving AI platform that explores, designs, and formally verifies chip architectures. It co-optimizes compilers, system software, runtimes, and models, collapsing the distance between model evolution and silicon deployment. Type: AI platform / service.

## Market Standing
- **Valuation**: Not disclosed
- **Key Metric**: Total Funding – $24M seed round (June 2026)
- **Notable Investors/Partners**: Kindred Ventures (lead), TQ Ventures (lead), Race Capital, Together Fund, plus angel investors Jeff Dean, Srinivas Narayanan, Lukasz Kaiser, Aravind Srinivas, Kunle Olokotun, Trevor Blackwell, Dr. Alex Wissner-Gross, and executives from NVIDIA, Google, OpenAI, Perplexity.
- **Growth Signals**: 
  - Raised $24M seed in June 2026 from top-tier investors.
  - Assembled an elite team of researchers and engineers from Anthropic, xAI, Google DeepMind, Meta, Intel, and Samsung.
  - Founders have backgrounds at Apple’s silicon teams and Tesla’s AI5 chip program; collectively the team has taped out 80+ production chips and managed multi-billion-dollar product lines.

## Competitive Advantages
- **First-principles approach**: Not adapting AI to legacy chip workflows but rebuilding the entire chip design process from scratch.
- **Provable verification**: AI system includes formal verification, reducing risk and iteration in chip design.
- **Convergent expertise**: Rare combination of frontier AI research and deep silicon design experience within the same team.
- **Self-improving system**: The platform learns from each design cycle, creating a flywheel of faster, better designs.

## Strategic Focus
- **Democratize custom chip co-design**: Make specialized silicon accessible beyond a handful of incumbents.
- **Shorten chip development cycles**: Move from multi-year cycles to software-like velocity.
- **Unified design space**: Enable synchronous optimization of models, compilers, runtimes, and hardware.

## Why Work Here
- **Frontier work**: Tackle one of the most ambitious problems in modern technology – AI-driven chip design.
- **Small, exceptional team**: Emphasis on ownership ("Surface Area"), relentless execution, and long-term craft.
- **Culture**: Values include depth, intellectual rigor, and rapid prototyping. Team members come from top AI and semiconductor labs.
- **Location/Policy**: Not explicitly stated; likely US-based with some flexibility. The careers page highlights a fully in-person culture for deep collaboration (inferred from "small team" and "end-to-end ownership"). 
- **Perks**: Not detailed, but the work involves cutting-edge research and infrastructure.

## Sources
1. [architectlabs.com](https://architectlabs.com/)
2. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/architect)
3. [linkedin.com](https://www.linkedin.com/company/architectlab)
4. [kindredventures.com](https://kindredventures.com/announcement/architect-labs-democratizing-custom-chip-co-design/)

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