---
title: 'Microarchitect / RTL Design - Network Datapath & MAC Engine at Architect Labs'
canonical: 'https://feeny.ai/job/microarchitect-rtl-design-network-datapath-mac-engine-architect-labs-palo-alto-pgg4djxk6n5q'
type: 'job'
last_seen: '2026-09-09'
---

# Microarchitect / RTL Design - Network Datapath & MAC Engine at Architect Labs

- **Company:** Architect Labs
- **Location:** Palo Alto, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-08-12
- **Last confirmed live:** 2026-09-09
- **Apply:** https://jobs.ashbyhq.com/architect/20be489b-5fc9-4470-ab06-730e013fcf5c

## Job description

## ABOUT ARCHITECT

Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new era of domain-specific chips that unlock capabilities impossible with current hardware paradigms. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel.

## WHAT YOU’LL DO

As a Founding Member of the Technical Staff on the RTL Design team at Architect, you’ll own the AI-driven microarchitecture and RTL design of high-performance networking subsystems going into production silicon. You will define, drive, and revise the block-level micro-architecture specification for Ethernet MAC engines, packet processing pipelines, and network datapath logic — ensuring line-rate performance, protocol compliance, and seamless SoC integration.

## CORE RESPONSIBILITIES

- Own the network datapath RTL end-to-end: from IEEE 802.3-compliant MAC engine design through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow.
- Design and implement Ethernet MAC engines: including 802.3 MAC/PCS layers, FCS generation/checking, flow control (802.3x pause, PFC), auto-negotiation state machines, and rate adaptation logic for multi-speed operation (10G/25G/50G/100G/400G+).
- Architect packet processing datapaths: including Tx/Rx FIFO management, packet buffering and scheduling, credit-based flow control, descriptor management, and DMA interfaces for host-to-network data movement.
- Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs (latency vs. throughput vs. area), and feed area/timing/power realities back into the architecture and internal AI systems.
- Define and maintain interface specifications: MII/GMII/XGMII/CGMII variants, AXI-Stream for packet data, AXI for CSR/DMA, and custom sideband signaling for scheduling and QoS.
- Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, regression flows, lint/CDC waivers, and integration collateral for the networking subsystem.
- Close collaboration with DV: Support verification bring-up with protocol-aware reference models, SVA assertions for protocol compliance, coverage plans targeting corner-case packet scenarios, and architectural documentation for verification closure.
- Close collaboration with SW and ML: Support and guide our SW and ML experts to revise and improve our in-house AI flow based on your networking domain expertise.
- Support FPGA prototyping on Xilinx for early functional validation of the network datapath, including interoperability testing with commercial PHYs and switches.

## WHAT WE’D LIKE TO SEE

## REQUIRED QUALIFICATIONS

- Degree: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
- Experience: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience involving networking or packet-processing silicon (NICs, switches, SmartNICs, or networking SoC subsystems).
- 802.3 Expertise: Deep familiarity with IEEE 802.3 Ethernet standards — MAC sublayer operation, PCS encoding (64b/66b, Reed-Solomon FEC), reconciliation sublayer, and multi-lane distribution/alignment.
- MAC Engine Design: Hands-on experience designing or owning Ethernet MAC blocks including Tx/Rx pipelines, inter-packet gap management, preamble/SFD processing, FCS computation, VLAN tagging, and jumbo frame support.
- SystemVerilog: Clear, synthesizable, lint-clean RTL with strong design habits — parameterization for multi-rate support, modularity for protocol layering, and configurability for different deployment targets.
- Packet Datapath Depth: Hands-on experience with packet buffering architectures, credit-based and descriptor-based DMA engines, store-and-forward vs. cut-through trade-offs, and scheduling/arbitration for network QoS.
- SoC Methodology: Solid grasp of synthesis, timing constraints, clock domain crossings (especially between MAC clock domains and core clocks), reset strategies, AMBA protocols (AXI, AXI-Stream), and power management.
- Python: Strong skills for design automation, regression infrastructure, protocol compliance test generation, and tooling.
- PPA Ownership: Experience taking a networking block from RTL through synthesis and working with PD teams on timing/area/power closure — particularly for high-frequency datapath logic.

## BONUS QUALIFICATIONS

- Experience with high-speed SerDes integration and PHY-side interfacing (CAUI, 56G/112G PAM4 SerDes).
- Familiarity with RDMA, RoCEv2, or TCP offload engine architectures.
- Experience with traffic management: scheduling algorithms (WRR, DWRR, strict priority), shaping, and policing.
- Low-power design techniques: clock gating for idle ports, power gating for unused lanes, multi-voltage domains.
- FPGA prototyping experience (Xilinx Vivado/Vitis), especially with Ethernet hard IPs or soft MAC cores.
- SVA assertions for protocol compliance checking (e.g., inter-frame gap, pause quanta timing, alignment marker lock).
- Prior IP building and delivery experience for Ethernet MAC/PCS or NIC subsystem blocks.
- Domain-specific research contributions: publications or patents in network-on-chip, datacenter networking, or high-performance packet processing hardware.

## WHY ARCHITECT

You’ll join a founding team building the future of chip design at the intersection of AI and silicon. Your networking expertise will directly shape production ASICs and influence how AI transforms hardware development — from spec to tapeout.

## About Architect Labs

## Company Overview
- **One-liner**: Architect Labs builds an AI system that explores, designs, and provably verifies custom chips for the world's most demanding AI workloads.
- **Entity Type**: Private (Seed stage – $24M raised)
- **Headquarters**: United States (specific city not publicly available)
- **Founded**: Not publicly available
- **Founders**: Ebrahim Hussain & Aaditya Subedi

## Core Business
- **Primary industry**: Semiconductor / AI chip design
- **Target customers**: B2B, Enterprise (companies needing custom silicon for frontier AI models)
- **Mission**: "Frontier AI for Silicon" – to enable custom chip co-design by rethinking the entire design process from first principles, accelerating development cycles and allowing organizations to own their hardware.

## Products & Services
- **AI-Driven Chip Co-Design System**: A self-improving AI platform that explores, designs, and formally verifies chip architectures. It co-optimizes compilers, system software, runtimes, and models, collapsing the distance between model evolution and silicon deployment. Type: AI platform / service.

## Market Standing
- **Valuation**: Not disclosed
- **Key Metric**: Total Funding – $24M seed round (June 2026)
- **Notable Investors/Partners**: Kindred Ventures (lead), TQ Ventures (lead), Race Capital, Together Fund, plus angel investors Jeff Dean, Srinivas Narayanan, Lukasz Kaiser, Aravind Srinivas, Kunle Olokotun, Trevor Blackwell, Dr. Alex Wissner-Gross, and executives from NVIDIA, Google, OpenAI, Perplexity.
- **Growth Signals**: 
  - Raised $24M seed in June 2026 from top-tier investors.
  - Assembled an elite team of researchers and engineers from Anthropic, xAI, Google DeepMind, Meta, Intel, and Samsung.
  - Founders have backgrounds at Apple’s silicon teams and Tesla’s AI5 chip program; collectively the team has taped out 80+ production chips and managed multi-billion-dollar product lines.

## Competitive Advantages
- **First-principles approach**: Not adapting AI to legacy chip workflows but rebuilding the entire chip design process from scratch.
- **Provable verification**: AI system includes formal verification, reducing risk and iteration in chip design.
- **Convergent expertise**: Rare combination of frontier AI research and deep silicon design experience within the same team.
- **Self-improving system**: The platform learns from each design cycle, creating a flywheel of faster, better designs.

## Strategic Focus
- **Democratize custom chip co-design**: Make specialized silicon accessible beyond a handful of incumbents.
- **Shorten chip development cycles**: Move from multi-year cycles to software-like velocity.
- **Unified design space**: Enable synchronous optimization of models, compilers, runtimes, and hardware.

## Why Work Here
- **Frontier work**: Tackle one of the most ambitious problems in modern technology – AI-driven chip design.
- **Small, exceptional team**: Emphasis on ownership ("Surface Area"), relentless execution, and long-term craft.
- **Culture**: Values include depth, intellectual rigor, and rapid prototyping. Team members come from top AI and semiconductor labs.
- **Location/Policy**: Not explicitly stated; likely US-based with some flexibility. The careers page highlights a fully in-person culture for deep collaboration (inferred from "small team" and "end-to-end ownership"). 
- **Perks**: Not detailed, but the work involves cutting-edge research and infrastructure.

## Sources
1. [architectlabs.com](https://architectlabs.com/)
2. [jobs.ashbyhq.com](https://jobs.ashbyhq.com/architect)
3. [linkedin.com](https://www.linkedin.com/company/architectlab)
4. [kindredventures.com](https://kindredventures.com/announcement/architect-labs-democratizing-custom-chip-co-design/)

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