--- title: 'Optical - Director, OE Development (DOD) at Eliyan' canonical: 'https://feeny.ai/job/optical-director-oe-development-dod-eliyan-bay-area-hn4sqg6j0g19' type: 'job' last_seen: '2026-09-07' --- # Optical - Director, OE Development (DOD) at Eliyan - **Company:** Eliyan - **Location:** Bay Area - **Employment:** full-time - **Work type:** onsite - **Posted:** 2026-07-02 - **Last confirmed live:** 2026-09-07 - **Apply:** https://jobs.lever.co/eliyan/f5e6f3c6-38fa-478f-a990-b49a127efdc3 ## Job description Eliyan is building NuLink, a proprietary die-to-die chiplet interconnect fabric purpose-built for AI infrastructure at hyperscale.  As Eliyan expands into co-packaged optics (CPO), the Director (or higher-level depending on experience) of Optical Product Development owns the product strategy for integrating third-party optical components — VCSELs, photodetectors, lenses, and fiber interfaces — with Eliyan's silicon die at the package level. This role requires deep familiarity with semiconductor fabrication and assembly processes, as all optical integration decisions are constrained by and executed within a semiconductor packaging environment. ## KEY RESPONSIBILITIES - Define optical product strategy centered on die-level co-packaging of external optical components with Eliyan's silicon. - Own the optical component selection and qualification process (VCSELs, PDs, lenses, fiber connectors), evaluating vendors against system performance and assembly compatibility requirements. - Drive assembly-aware optical product specifications — accounting for flip-chip tolerances, solder reflow constraints, alignment accuracy, and packaging design rules. - Engage silicon process and design teams on equal footing, translating optical requirements into process-compatible constraints and vice versa. - Navigate optical-electrical co-design tradeoffs within foundry process boundaries (e.g., TSMC, GlobalFoundries, or equivalent). - Serve as the primary interface between optical and silicon teams (analog/digital), ensuring bidirectional feed-in/feedback between optical integration requirements and silicon design. - Partner with Marketing to define product positioning, customer-facing optical specifications, and roadmap priorities. - Report execution status and product milestones to the COA ## QUALIFICATIONS - 12+ years in optical systems or photonic integration, with substantial hands-on experience in semiconductor fabrication, assembly, or advanced packaging environments. - Solid working knowledge of semiconductor fabrication processes — FEOL/BEOL concepts, lithography constraints, metal layer stackups, and how process design rules affect optical integration feasibility. - Deep understanding of co-packaging architectures — flip-chip bonding, micro-bump interconnects, interposer-based integration, or equivalent. - Experience qualifying and integrating third-party optical components (VCSELs, PDs, optical subassemblies) into semiconductor packages. - Familiarity with packaging design rules and their implications for optical alignment yield. - Experience navigating optical-electrical co-design tradeoffs within foundry process boundaries. - Strong cross-functional communication skills across silicon, packaging, and marketing teams. - Standards-body experience (IEEE 802.3, OIF, CPO Consortium) a plus. ## About Eliyan ## Company Overview - **One-liner**: Eliyan develops high-bandwidth, low-power chiplet interconnect technology (NuLink) that solves data bottlenecks in AI and data center chips. - **Entity Type**: Private (Series C-II) - **Headquarters**: Santa Clara, California, United States - **Founded**: 2021 - **Founders**: Ramin Farjadrad (CEO), Syrus Ziai (VP Engineering), Patrick Soheili (Chief Strategy & Business Officer) ## Core Business - Primary industry: Semiconductor Manufacturing (chiplet interconnect IP and PHY silicon) - Target customers: B2B – companies building custom AI chips (hyperscalers, chip designers, networking firms) - Mission: “Revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.” ## Products & Services - **[NuLink™ D2D PHY](https://eliyan.com/about/)**: Die-to-die interconnect PHY supporting industry standards (BoW and UCIe) and proprietary simultaneous-bidirectional (SBD) technology. Delivers 4× the bandwidth and 2× the power efficiency of alternatives in advanced or standard packaging, with bump pitches from 40–130 microns. - **[NuLink™-XD](https://linkedin.com/company/eliyan-corporation)**: A new class of power-reach configurable 224G PAM4 SerDes for chip-to-chip and chip-to-module applications, targeting the lowest-power electro-optical modules for AI scale-up networks. Up to 40% lower power than competing solutions. ## Market Standing - **Valuation**: $1 billion (as of July 2026 Series C) - **Annual Revenue**: $3.5 million (2025); forecasts hundreds of millions by end of 2027 [reuters.com](https://www.cbinsights.com/company/eliyan) - **Total Funding**: $295 million (conflicting reports: other sources state $150M total); includes $145M Series C led by Seligman Ventures (July 2026), $60M Series B led by Samsung Catalyst Fund and Tiger Global (March 2024), $40M Series A led by Tracker Capital (Nov 2022). - **Notable Investors/Partners**: Seligman Ventures (board seat for Umesh Padval), Cisco Systems, Lumentum, Samsung Catalyst Fund, Tiger Global Management, Tracker Capital, VentureTech Alliance. - **Growth Signals**: Headcount of 73 employees with +6.7% monthly growth; 21 active job postings (quarterly trend +2,000%); expects to start chiplet shipments in 2026; expanding across 6 countries (US, Germany, Netherlands, Canada, India, Israel). ## Competitive Advantages - Breakthrough die-to-die interconnect architecture (invented by founder Ramin Farjadrad in 2016) that achieves 4× bandwidth and 2× power efficiency versus competing IP. - Works with standard packaging (wide range of bump pitches), reducing cost and complexity for chip designers. - Independent alternative to Broadcom/Marvell in the chiplet interconnect space, giving custom AI chip makers a neutral, high-performance option. ## Strategic Focus - Solving the growing data-movement bottleneck in AI compute (GPUs often idle 30–40% waiting for data). - Scaling NuLink and NuLink-XD platforms to support both chip-to-chip and chip-to-module applications for next-generation AI infrastructure. - Ramping chiplet production and licensing revenue, targeting hundreds of millions in sales by 2027. ## Why Work Here - On-site culture with offices in Santa Clara (HQ), Vancouver (BC), and other global locations; no remote/hybrid mentioned. - Engineering-heavy team (54% technical roles) with a fast-paced startup environment and deep expertise from companies like Marvell, Intel, AMD, and Synopsys. - Opportunity to work on cutting-edge semiconductor interconnect technology that directly impacts AI performance. - Active hiring across digital design, verification, DFT, physical design, optical engineering, and program management. ## Sources 1. [eliyan.com/about](https://eliyan.com/about/) 2. [jobs.lever.co/eliyan](https://jobs.lever.co/eliyan) 3. [linkedin.com/company/eliyan-corporation](https://linkedin.com/company/eliyan-corporation) 4. [cbinsights.com/company/eliyan](https://www.cbinsights.com/company/eliyan) 5. [reuters.com (via CNA)](https://www.cbinsights.com/company/eliyan) (Note: embedded Reuters article on CB Insights page) 6. [eliyan.com/careers](https://eliyan.com/careers/) ## Other roles at Eliyan - [Program Management - Principal / Sr. Principal Technical Program Manager – IP, ASIC & Chiplet Platforms](https://feeny.ai/job/program-management-principal-sr-principal-technical-program-manager-ip-asic-29s06vbpaq89) — Bay Area - [Program Management - Principal TPM – Packaging, SI/PI & System Integration](https://feeny.ai/job/program-management-principal-tpm-packaging-si-pi-system-integration-eliyan-bay-2dhawebwestt) — Bay Area - [Silicon Validation, Test & Characterization Engineer (title will reflect experience)](https://feeny.ai/job/silicon-validation-test-characterization-engineer-title-will-reflect-experience-9n726paagrw8) — Bay Area - [DV - Staff (+) Verification Engineer -  AMS modeling](https://feeny.ai/job/dv-staff-verification-engineer-ams-modeling-eliyan-bay-area-vancouver-canada-27k4khnvjx3y) — Bay Area / Vancouver, Canada / Toronto, Canada - [PD - Sr Staff - Physical Verification Lead | Signoff & DRC](https://feeny.ai/job/pd-sr-staff-physical-verification-lead-signoff-drc-eliyan-bay-area-jmkanxqtq810) — Bay Area - [PD - Sr Staff — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |](https://feeny.ai/job/pd-sr-staff-cad-design-methodology-rtl-to-gdsii-flow-advanced-node-methodology-gtnhek1texp8) — Bay Area - [DV - Principal Digital Verification Engineer](https://feeny.ai/job/dv-principal-digital-verification-engineer-eliyan-vancouver-bc-or-bay-area-jttvf7k0jdc6) — Vancouver Bc OR Bay Area, CA - [DV - Staff Verification Engineer - Serdes](https://feeny.ai/job/dv-staff-verification-engineer-serdes-eliyan-bay-area-vancouver-canada-toronto-3sesn9ej7d97) — Bay Area / Vancouver, Canada / Toronto, Canada - [Photonics IC Validation and Characterization Engineer (title will reflect experience)](https://feeny.ai/job/photonics-ic-validation-and-characterization-engineer-title-will-reflect-kj77ht3q4rp9) — Bay Area - [Digital - SerDes Digital Design Lead](https://feeny.ai/job/digital-serdes-digital-design-lead-eliyan-bay-area-6mznhxayfytd) — Bay Area