---
title: 'PD - Sr Staff  — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology | at Eliyan'
canonical: 'https://feeny.ai/job/pd-sr-staff-cad-design-methodology-rtl-to-gdsii-flow-advanced-node-methodology-gtnhek1texp8'
type: 'job'
last_seen: '2026-09-07'
---

# PD - Sr Staff  — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology | at Eliyan

- **Company:** Eliyan
- **Location:** Bay Area
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-05-11
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.lever.co/eliyan/4c74e7c0-5215-4cee-996d-d7c689ee9f5f

## Job description

## ABOUT THE ROLE

As a Sr Staff / Principal CAD & Design Methodology Engineer, you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You will define and deploy multi-vendor, multi-foundry design methodology platforms, lead hierarchical SoC implementation strategies, and drive low-power chiplet products. You will own the R2G (RTL-to-GDSII) system architecture spanning Intel, TSMC, Samsung, and GlobalFoundries nodes — enabling scalable, high-quality tapeouts across diverse product classes.

## KEY RESPONSIBILITIES

RTL-to-GDSII Flow Architecture & Development

- Architect, develop, and maintain a comprehensive RTL-to-GDSII digital implementation flow supporting multi-level hierarchical SoC designs using both top-down and bottom-up methodologies.
- Define R2G flow architecture that integrates best-in-class EDA tools from Synopsys, Cadence, and Siemens — enabling a vendor-agnostic, extensible platform adaptable to evolving foundry PDKs.
- Design the Reference Design and Validation Platform (RDVP) to enable continuous RTL-to-GDSII flow development, regression, and qualification across technology nodes.
- Define design rules, constraint templates, and implementation guidelines specific to each foundry node — ensuring teams adopt correct methodology from project kickoff through tapeout.
- Collaborate with foundry technology teams at Intel Foundry, TSMC, Samsung, and GlobalFoundries to stay ahead of node-specific methodology requirements and PDK updates.
- Lead methodology and execution for low-power core design targeting aggressive PPA targets in accelerator product lines — covering power intent definition, multi-voltage domain management, and clock gating strategy.
- Define and implement CPF/UPF-based low-power flows — covering level-shifter insertion, isolation cell placement, retention register strategy, and power domain crossings verification.
- Own EM/IR methodology for low-power multi-core designs — defining PDN architecture, power strapping strategies, and EM-clean routing guidelines per foundry requirements.
- Architect hierarchical design planning methodology for large, complex SoC designs — defining partition boundaries, interface timing budgets, pin assignment constraints, and hierarchical timing models (ETMs/ILMs).
- Lead top-level and block-level floorplan development — driving macro placement, power domain definition, IO ring planning, and die size optimization for PPA.
- Define and enforce hierarchical constraints — ensuring block-level implementations are physically and electrically compatible at integration, minimizing top-level ECO iterations.
- Define and own comprehensive clocking methodology covering Clock Mesh, Spine-and-Rib, H-Tree, and hybrid topologies — selecting the optimal strategy per design class, frequency target, and power budget.
- Develop custom clock cell libraries and constraints to support low-skew, low-power clock distributions across large multi-core SoCs.
- Define system architecture to leverage external EDA ecosystem tools and methods — accelerating alignment with vendor solutions and reducing new-node bring-up time.
- Define logic synthesis methodology — specifying SDC constraint authoring guidelines, multi-corner multi-mode (MCMM) synthesis strategies, and design-for-test (DFT) integration points.
- Own static timing analysis (STA) methodology — defining corner selection, OCV/AOCV/POCV derate strategies, timing exception management, and hold/setup
- Drive continuous improvement of CAD infrastructure through automation, ML-assisted optimization, and adoption of emerging EDA capabilities.

## MINIMUM QUALIFICATIONS

- 15+ years of experience in ASIC CAD, design methodology, or physical design with a proven record of leading multi-node, multi-foundry platform deployments.
- Demonstrated success deploying R2G platforms across multiple external foundry nodes (TSMC N3/N5/N7, Samsung SF3/SF4, GlobalFoundries GF12/GF22).
- Deep expertise in low-power design methodology — UPF/CPF flows, multi-voltage domain integration, retention strategy, and power domain verification.
- Proven expertise in clocking methodologies: Clock Mesh, Spine-and-Rib, H-Tree, and hybrid clock architectures with custom cell integration.
- Familiarity with chiplet and 2.5D integration methodology — die-to-die interface timing, UCIe/BoW PHY integration, and hierarchical top-level assembly flows.
- Exceptional problem-solving ability and communication skills — comfortable presenting to executive leadership and engaging directly with foundry technology teams.

## About Eliyan

## Company Overview
- **One-liner**: Eliyan develops high-bandwidth, low-power chiplet interconnect technology (NuLink) that solves data bottlenecks in AI and data center chips.
- **Entity Type**: Private (Series C-II)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2021
- **Founders**: Ramin Farjadrad (CEO), Syrus Ziai (VP Engineering), Patrick Soheili (Chief Strategy & Business Officer)

## Core Business
- Primary industry: Semiconductor Manufacturing (chiplet interconnect IP and PHY silicon)
- Target customers: B2B – companies building custom AI chips (hyperscalers, chip designers, networking firms)
- Mission: “Revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.”

## Products & Services
- **[NuLink™ D2D PHY](https://eliyan.com/about/)**: Die-to-die interconnect PHY supporting industry standards (BoW and UCIe) and proprietary simultaneous-bidirectional (SBD) technology. Delivers 4× the bandwidth and 2× the power efficiency of alternatives in advanced or standard packaging, with bump pitches from 40–130 microns.
- **[NuLink™-XD](https://linkedin.com/company/eliyan-corporation)**: A new class of power-reach configurable 224G PAM4 SerDes for chip-to-chip and chip-to-module applications, targeting the lowest-power electro-optical modules for AI scale-up networks. Up to 40% lower power than competing solutions.

## Market Standing
- **Valuation**: $1 billion (as of July 2026 Series C)
- **Annual Revenue**: $3.5 million (2025); forecasts hundreds of millions by end of 2027 [reuters.com](https://www.cbinsights.com/company/eliyan)
- **Total Funding**: $295 million (conflicting reports: other sources state $150M total); includes $145M Series C led by Seligman Ventures (July 2026), $60M Series B led by Samsung Catalyst Fund and Tiger Global (March 2024), $40M Series A led by Tracker Capital (Nov 2022).
- **Notable Investors/Partners**: Seligman Ventures (board seat for Umesh Padval), Cisco Systems, Lumentum, Samsung Catalyst Fund, Tiger Global Management, Tracker Capital, VentureTech Alliance.
- **Growth Signals**: Headcount of 73 employees with +6.7% monthly growth; 21 active job postings (quarterly trend +2,000%); expects to start chiplet shipments in 2026; expanding across 6 countries (US, Germany, Netherlands, Canada, India, Israel).

## Competitive Advantages
- Breakthrough die-to-die interconnect architecture (invented by founder Ramin Farjadrad in 2016) that achieves 4× bandwidth and 2× power efficiency versus competing IP.
- Works with standard packaging (wide range of bump pitches), reducing cost and complexity for chip designers.
- Independent alternative to Broadcom/Marvell in the chiplet interconnect space, giving custom AI chip makers a neutral, high-performance option.

## Strategic Focus
- Solving the growing data-movement bottleneck in AI compute (GPUs often idle 30–40% waiting for data).
- Scaling NuLink and NuLink-XD platforms to support both chip-to-chip and chip-to-module applications for next-generation AI infrastructure.
- Ramping chiplet production and licensing revenue, targeting hundreds of millions in sales by 2027.

## Why Work Here
- On-site culture with offices in Santa Clara (HQ), Vancouver (BC), and other global locations; no remote/hybrid mentioned.
- Engineering-heavy team (54% technical roles) with a fast-paced startup environment and deep expertise from companies like Marvell, Intel, AMD, and Synopsys.
- Opportunity to work on cutting-edge semiconductor interconnect technology that directly impacts AI performance.
- Active hiring across digital design, verification, DFT, physical design, optical engineering, and program management.

## Sources
1. [eliyan.com/about](https://eliyan.com/about/)
2. [jobs.lever.co/eliyan](https://jobs.lever.co/eliyan)
3. [linkedin.com/company/eliyan-corporation](https://linkedin.com/company/eliyan-corporation)
4. [cbinsights.com/company/eliyan](https://www.cbinsights.com/company/eliyan)
5. [reuters.com (via CNA)](https://www.cbinsights.com/company/eliyan) (Note: embedded Reuters article on CB Insights page)
6. [eliyan.com/careers](https://eliyan.com/careers/)

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