---
title: 'PD - Sr Staff - Physical Verification Lead | Signoff & DRC at Eliyan'
canonical: 'https://feeny.ai/job/pd-sr-staff-physical-verification-lead-signoff-drc-eliyan-bay-area-jmkanxqtq810'
type: 'job'
last_seen: '2026-09-14'
---

# PD - Sr Staff - Physical Verification Lead | Signoff & DRC at Eliyan

- **Company:** Eliyan
- **Location:** Bay Area
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-05-11
- **Last confirmed live:** 2026-09-14
- **Apply:** https://jobs.lever.co/eliyan/2a0ab8c8-555c-41f2-a117-1072d8892323

## Job description

## ABOUT THE ROLE

As a Sr Staff / Principal CAD & Design Methodology Engineer, you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You will define and deploy multi-vendor, multi-foundry design methodology platforms, lead hierarchical SoC implementation strategies, and drive low-power chiplet products. You will own the R2G (RTL-to-GDSII) system architecture spanning Intel, TSMC, Samsung, and GlobalFoundries nodes — enabling scalable, high-quality tapeouts across diverse product classes.

## KEY RESPONSIBILITIES

Signoff Physical Verification — Top Level

- Own end-to-end physical verification signoff strategy from block level through chip top, ensuring all DRC, LVS, ERC, and antenna violations are cleanly resolved before tapeout.
- Define and execute hierarchical DRC methodology across multiple abstraction levels (block, partition, top), leveraging Calibre or IC Validator in hierarchical and distributed modes.
- Drive full-chip DRC convergence across advanced nodes including 28nm, 22nm, 14nm, 7nm, 5nm, 3nm, and 2nm at Intel, TSMC, Samsung, and GlobalFoundries.
- Develop waiver management processes with foundry sign-off teams; distinguish hard violations from soft DFM advisories and document justifications for each waiver class.
- Collaborate with physical design teams on real-time DRC closure, guiding routing rules, spacing constraints, and metal fill strategies to minimize violations upstream.
- Lead bump planning for flip-chip and 2.5D/3D chiplet assemblies — define bump array configuration, pitch, UBM sizing, and RDL routing to satisfy both electrical and mechanical requirements.
- Execute top-level bump DRC checks including bump pitch, clearance, RDL spacing, keep-out zones, and passivation opening rules per foundry and OSAT PDK requirements.
- Validate bump-to-bump, bump-to-signal, and bump-to-power domain spacing across multiple power domains and IO ring configurations.
- Collaborate with package and substrate teams on co-design constraints to align die-side bump map with package-side ball grid array (BGA) and interposer routing.
- Ensure compliance with electromigration (EM) limits on bump current density and perform IR-drop correlation between die and package.
- Develop and maintain Calibre SVRF/TVF and IC Validator runsets customized per foundry PDK, managing layer name mappings, derived layers, and rule deck versioning.
- Implement incremental and cell-level DRC methodologies to accelerate design iteration turnaround — reducing full-chip DRC runtime by leveraging hierarchical cell reuse.
- Drive LVS signoff at all levels of the design hierarchy, establishing schematic-vs-layout equivalence across mixed-signal, standard cell, memory, and custom analog blocks.
- Own ERC (Electrical Rules Check) signoff including antenna, floating gate, and latch-up checks across full-chip context.
- Lead DFM signoff including critical area analysis (CAA), CMP density checks, and foundry-required DFM rule checks — prioritize and resolve _c (critical) violations before tapeout.
- Build and maintain robust PV automation infrastructure using Python, Perl, and Tcl — automate runset selection, job dispatch, result parsing, and signoff reporting.
- Present PV status, waiver summaries, and signoff readiness reports to executive leadership and foundry partners at tapeout reviews.

## MINIMUM QUALIFICATIONS

- 15+ years of ASIC physical verification experience with a proven track record of leading tapeouts at advanced nodes.
- Deep multi-foundry expertise across two or more of: Intel Foundry (18A/20A), TSMC (N2–N7), Samsung (SF3–SF5), GlobalFoundries (GF12/GF22).
- Multi-node experience spanning 28nm through 2nm, with strong knowledge of how DRC rule complexity evolves across nodes.
- Proven expertise in bump planning and package-level DRC for flip-chip, CoWoS, EMIB, Foveros, technologies.
- Experience with advanced packaging co-design flows integrating die-level GDSII with package substrate databases.
- Strong understanding of DFM concepts: critical area, CMP density, RDL reliability, and litho-aware design.
- Experience building and maintaining DRC regression infrastructure with automated trending and signoff dashboards.
- Familiarity with 2.5D/3D chiplet integration challenges — die-to-die connectivity DRC, TSV keep-out, and heterogeneous integration rule decks.
- Excellent communication and cross-functional collaboration skills — ability to work with design, package, and foundry teams simultaneously.

## About Eliyan

## Company Overview
- **One-liner**: Eliyan develops high-bandwidth, low-power chiplet interconnect technology (NuLink) that solves data bottlenecks in AI and data center chips.
- **Entity Type**: Private (Series C-II)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2021
- **Founders**: Ramin Farjadrad (CEO), Syrus Ziai (VP Engineering), Patrick Soheili (Chief Strategy & Business Officer)

## Core Business
- Primary industry: Semiconductor Manufacturing (chiplet interconnect IP and PHY silicon)
- Target customers: B2B – companies building custom AI chips (hyperscalers, chip designers, networking firms)
- Mission: “Revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.”

## Products & Services
- **[NuLink™ D2D PHY](https://eliyan.com/about/)**: Die-to-die interconnect PHY supporting industry standards (BoW and UCIe) and proprietary simultaneous-bidirectional (SBD) technology. Delivers 4× the bandwidth and 2× the power efficiency of alternatives in advanced or standard packaging, with bump pitches from 40–130 microns.
- **[NuLink™-XD](https://linkedin.com/company/eliyan-corporation)**: A new class of power-reach configurable 224G PAM4 SerDes for chip-to-chip and chip-to-module applications, targeting the lowest-power electro-optical modules for AI scale-up networks. Up to 40% lower power than competing solutions.

## Market Standing
- **Valuation**: $1 billion (as of July 2026 Series C)
- **Annual Revenue**: $3.5 million (2025); forecasts hundreds of millions by end of 2027 [reuters.com](https://www.cbinsights.com/company/eliyan)
- **Total Funding**: $295 million (conflicting reports: other sources state $150M total); includes $145M Series C led by Seligman Ventures (July 2026), $60M Series B led by Samsung Catalyst Fund and Tiger Global (March 2024), $40M Series A led by Tracker Capital (Nov 2022).
- **Notable Investors/Partners**: Seligman Ventures (board seat for Umesh Padval), Cisco Systems, Lumentum, Samsung Catalyst Fund, Tiger Global Management, Tracker Capital, VentureTech Alliance.
- **Growth Signals**: Headcount of 73 employees with +6.7% monthly growth; 21 active job postings (quarterly trend +2,000%); expects to start chiplet shipments in 2026; expanding across 6 countries (US, Germany, Netherlands, Canada, India, Israel).

## Competitive Advantages
- Breakthrough die-to-die interconnect architecture (invented by founder Ramin Farjadrad in 2016) that achieves 4× bandwidth and 2× power efficiency versus competing IP.
- Works with standard packaging (wide range of bump pitches), reducing cost and complexity for chip designers.
- Independent alternative to Broadcom/Marvell in the chiplet interconnect space, giving custom AI chip makers a neutral, high-performance option.

## Strategic Focus
- Solving the growing data-movement bottleneck in AI compute (GPUs often idle 30–40% waiting for data).
- Scaling NuLink and NuLink-XD platforms to support both chip-to-chip and chip-to-module applications for next-generation AI infrastructure.
- Ramping chiplet production and licensing revenue, targeting hundreds of millions in sales by 2027.

## Why Work Here
- On-site culture with offices in Santa Clara (HQ), Vancouver (BC), and other global locations; no remote/hybrid mentioned.
- Engineering-heavy team (54% technical roles) with a fast-paced startup environment and deep expertise from companies like Marvell, Intel, AMD, and Synopsys.
- Opportunity to work on cutting-edge semiconductor interconnect technology that directly impacts AI performance.
- Active hiring across digital design, verification, DFT, physical design, optical engineering, and program management.

## Sources
1. [eliyan.com/about](https://eliyan.com/about/)
2. [jobs.lever.co/eliyan](https://jobs.lever.co/eliyan)
3. [linkedin.com/company/eliyan-corporation](https://linkedin.com/company/eliyan-corporation)
4. [cbinsights.com/company/eliyan](https://www.cbinsights.com/company/eliyan)
5. [reuters.com (via CNA)](https://www.cbinsights.com/company/eliyan) (Note: embedded Reuters article on CB Insights page)
6. [eliyan.com/careers](https://eliyan.com/careers/)

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