---
title: 'Physical Design Engineer at Delos Data Inc'
canonical: 'https://feeny.ai/job/physical-design-engineer-delos-data-inc-remote-y6hzv0vsjjdr'
type: 'job'
last_seen: '2026-09-15'
---

# Physical Design Engineer at Delos Data Inc

- **Company:** Delos Data Inc
- **Location:** Remote
- **Employment:** full-time
- **Work type:** remote
- **Posted:** 2026-09-10
- **Last confirmed live:** 2026-09-15
- **Apply:** https://jobs.ashbyhq.com/delos-data/b954d6d7-a27d-4669-be97-5070190345d8

## Job description

What We Need: We are looking for a Principal Physical Design Engineer to serve as an early member of our physical design team. You will own some of the most challenging physical implementation problems in the design, drive critical blocks and top-level integration, and help establish the methodologies required to achieve performance, power, area, and schedule targets. This is a deeply hands-on role for an engineer who can independently take complex designs from floorplan through signoff, solve difficult timing and implementation problems, and provide technical leadership across the broader physical design team. Key Responsibilities:

- Own physical implementation of complex blocks and subsystems from synthesized netlist through signoff.
- Develop floorplans considering hierarchy, macros, interfaces, congestion, timing, power, and routability.
- Develop and optimize power-grid implementations and support IR-drop and electromigration closure.
- Drive placement, optimization, clock-tree synthesis, routing, extraction, timing closure, and ECO implementation.
- Own difficult setup, hold, signal-integrity, congestion, and physical implementation problems.
- Lead timing closure across block boundaries and support top-level timing convergence.
- Perform and drive static timing analysis across multiple modes and corners.
- Support signal-integrity analysis and timing impact from crosstalk, variation, and physical effects.
- Drive physical signoff, including DRC, LVS, antenna, density, connectivity, and related physical verification requirements.
- Perform or support power integrity analysis, including static and dynamic IR drop and electromigration.
- Develop implementation strategies for high-performance and physically challenging portions of the design.
- Partner with RTL and architecture teams to identify implementation problems early and recommend architectural or logical changes where appropriate.
- Work closely with DFT, verification, package, SI/PI, and other engineering teams to resolve cross-functional design issues.
- Develop and improve physical design flows, scripts, automation, metrics, and methodologies.
- Evaluate implementation results and identify opportunities to improve PPA, runtime, convergence, and design quality.
- Provide technical guidance and mentorship to other physical design engineers.
- Participate in design reviews, methodology reviews, and tapeout readiness assessments.
- Serve as a technical escalation point for complex physical design and signoff issues.

Required Skills and Qualifications:

- 10+ years of ASIC or SoC physical design experience with multiple successful tapeouts.
- Expert-level understanding of floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification.
- Strong expertise in static timing analysis and multi-mode, multi-corner timing closure.
- Strong understanding of power delivery, IR drop, electromigration, and signal integrity.
- Demonstrated ability to independently own complex blocks or major portions of a chip through signoff.
- Strong understanding of clock design, timing constraints, variation, extraction, and advanced-node physical effects.
- Experience with industry-standard Cadence and/or Synopsys physical implementation and signoff tools.
- Strong scripting and automation skills using Tcl, Python, Perl, or similar languages.
- Ability to debug complex design problems across RTL, timing, physical implementation, and signoff domains.
- Strong communication skills and ability to provide technical leadership without requiring formal management authority.

Desired Skills:

- Experience with advanced process nodes.
- Experience with large, high-frequency or highly interconnected semiconductor designs.
- Experience with hierarchical design and top-level physical integration.
- Experience developing physical design methodologies and automation.
- Experience working closely with package, SI/PI, and power-delivery teams.
- Experience with multi-die, chiplet, or advanced packaging architectures.
- Familiarity with EDA tool evaluation, benchmarking, and optimization.
- Experience in an early-stage semiconductor environment.

Additional Requirements:

- Ability to independently drive complex technical problems to closure.
- Comfortable operating across both detailed implementation work and broader chip-level design considerations.
- Ability to work effectively in a highly collaborative, fast-paced engineering organization.

Compensation: Target base salary for this role is $180,000 – $260,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location. We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics. Agency Note: We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.

## #LI-EW1

## About Delos Data Inc

## Company Overview
- **One-liner**: Delos Data builds a new interconnect architecture and server design purpose-built for AI inference, enabling faster, more scalable inference by eliminating network bottlenecks.
- **Entity Type**: Private (Stealth/Seed stage)
- **Headquarters**: Palo Alto, California, USA
- **Founded**: 2025
- **Founders**: Ed Doe (CEO & Co-Founder), Dan Daly (CTO & Co-Founder)

## Core Business
- **Primary Industry**: Semiconductor Manufacturing / AI Infrastructure
- **Target Customers**: Hyperscalers, AI infrastructure builders, and enterprises scaling AI inference workloads (B2B)
- **Mission/Purpose**: To deliver the world's most capable and responsive intelligence by building an interconnect purpose-built for AI inference, not borrowed from HPC, cloud, or training.

## Products & Services
- **Nonstop AI™**: A new cluster architecture and server design that accelerates AI inference through cabled scale-up. It reduces GPU idle time caused by data center interconnect bottlenecks and is designed to flexibly scale to thousands of GPUs, CPUs, and accelerators.
- **Delos Server**: Brings scale-up IO to the network fabric, enabling larger scale-up domains for inference.
- **Delos Mosaic™**: Software providing fine-grained visibility into the scale-up domain, allowing for real-time inference bottleneck detection and AI workload tuning.

## Market Standing
- **Valuation**: Not publicly disclosed (Private, early-stage company)
- **Key Metric**: Total funding not publicly disclosed; company is in early access deployment with select customers.
- **Notable Investors/Partners**: Not publicly disclosed; company exhibited at NVIDIA GTC 2026 (Booth 150) and will demonstrate at Computex 2026 (Booth J1328).
- **Growth Signals**: 
  - Founded in 2025, already has 3 employees with 25% monthly headcount growth.
  - 7 active job postings as of mid-2026.
  - Announced Nonstop AI™ architecture in May 2026 with early access deployments.
  - Exhibited at major industry events (NVIDIA GTC 2026, Computex 2026).
  - Website traffic growing 39.4% month-over-month.

## Competitive Advantages
- **Purpose-built for inference**: Unlike competitors who borrow interconnects from HPC, cloud, or training, Delos Data builds an interconnect specifically designed for AI inference workloads.
- **Cabled scale-up architecture**: Enables flexible scaling to thousands of GPUs, CPUs, and accelerators, reducing GPU idle time caused by network bottlenecks.
- **Full-stack approach**: Combines hardware (Delos Server), software (Delos Mosaic™), and silicon expertise to deliver a unified system-level solution.
- **Ecosystem compatibility**: Built to work within today's GPU and accelerator ecosystems, making adoption easier for hyperscalers and enterprises.
- **Founding team pedigree**: CTO Dan Daly and CEO Ed Doe bring deep expertise from leading semiconductor and AI companies.

## Strategic Focus
- **Product launch and market entry**: Currently in early access with select customers, with broader availability planned for Q4 2026.
- **Scaling the team**: Actively hiring across engineering (system software, DFT, verification, SDET), advanced packaging, and people operations roles.
- **Building the brand**: Establishing presence at major industry events (NVIDIA GTC, Computex) to build credibility and attract top talent.
- **Targeting hyperscalers and AI infrastructure builders**: The primary customer base for the Nonstop AI™ architecture.

## Why Work Here
- **Mission-driven work**: Opportunity to build foundational infrastructure for the next generation of AI, working on a problem the founders describe as "the next leap in AI performance."
- **Early-stage impact**: Join a company founded in 2025 with only 3 employees, offering significant ownership and influence over product and culture.
- **Hybrid/Remote flexibility**: Roles are listed as both remote and hybrid (Palo Alto, CA and Montréal, QC, CAN), with a "Remote Workspace" designation for many positions.
- **Founding team**: Work directly under experienced leadership (CTO Dan Daly, CEO Ed Doe) with deep expertise in semiconductors and AI.
- **Cutting-edge tech stack**: Work with Kubernetes, PyTorch, CUDA, SystemVerilog, Python, Terraform, and more across hardware and software domains.
- **High-growth trajectory**: 25% monthly headcount growth, active hiring across 7+ roles, and strong momentum from major industry events.

## Sources
1. [delosdata.com](https://delosdata.com/)
2. [builtin.com](https://builtin.com/company/delos-data)
3. [linkedin.com](https://www.linkedin.com/company/delosdata)
4. [delosdata.com/press](https://www.delosdata.com/press/faster-ai-inference-enabled-by-1000x-higher-scale-with-delos-data-nonstop-ai)
5. [opencorpdata.com](https://opencorpdata.com/us-va/11860584)

## Other roles at Delos Data Inc

- [SerDes Validation Leader](https://feeny.ai/job/serdes-validation-leader-delos-data-inc-remote-cgr5a14pkbw8)
- [Principal AMS Design](https://feeny.ai/job/principal-ams-design-delos-data-inc-taiwan-j56g64ktnsvy) — Taiwan
- [Software Development Engineer in Test - AI](https://feeny.ai/job/software-development-engineer-in-test-ai-delos-data-inc-charlottesville-qftkz7gwjb6p) — Charlottesville, VA
- [Software Development Engineer in Test - AI](https://feeny.ai/job/software-development-engineer-in-test-ai-delos-data-inc-palo-alto-h0zdwvb7hn1r) — Palo Alto, CA
- [System Software Engineer - AI](https://feeny.ai/job/system-software-engineer-ai-delos-data-inc-palo-alto-xcxcygvyxje5) — Palo Alto, CA
- [Principal Power Design Engineer](https://feeny.ai/job/principal-power-design-engineer-delos-data-inc-palo-alto-k4t1g4pn932e) — Palo Alto, CA
- [Package Engineer](https://feeny.ai/job/package-engineer-delos-data-inc-palo-alto-0jq1ejpayss3) — Palo Alto, CA
- [Senior Electrical Engineer, Server Hardware 資深伺服器硬體工程師](https://feeny.ai/job/senior-electrical-engineer-server-hardware-delos-data-inc-taiwan-vvrpb87n5qrv) — Taiwan
- [DFT Engineer](https://feeny.ai/job/dft-engineer-delos-data-inc-remote-gb8zfx61v80h)
- [Join the Delos Team!](https://feeny.ai/job/join-the-delos-team-delos-data-inc-remote-1ka64cpztr4b)