---
title: 'Physical Design Engineer - Flow & Methodologies at Etched'
canonical: 'https://feeny.ai/job/physical-design-engineer-flow-methodologies-etched-san-jose-3mcay1erbyft'
type: 'job'
last_seen: '2026-09-07'
---

# Physical Design Engineer - Flow & Methodologies at Etched

- **Company:** [Etched](https://feeny.ai/companies/etched)
- **Location:** San Jose, CA
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-07-23
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.ashbyhq.com/etched/d8ee2a43-d5be-47f0-9c89-f7a39bb9db0d

## Job description

## About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Methodology Engineer, you will architect our PD flow from first principles. You will own the infrastructure that allows our design team to iterate at unprecedented speeds, directly accelerating our time-to-market and enabling PPA gains that aren't possible with off-the-shelf CAD methodologies.

## Key Responsibilities

- Architect, build, and maintain our automated RTL-to-GDSII flow, from synthesis through place and route to signoff handoff.
- Automate PD flows end to end, including regression running, run management, and release and version control of flow configurations.
- Build and own the CAD infrastructure supporting PD, including tool version qualification and deployment, and efficient use of compute and licenses.
- Drive dashboards that show the convergence of projects related to PD, including timing, physical verification, and utilization trends.
- Optimize tool flows and work with EDA vendors to evaluate and incorporate the latest features.
- Define reference flows, QoR targets, and delivery checklists for 3rd party physical design services, and audit deliveries against them.
- Partner with block and top-level owners to debug flow issues and encode fixes into the methodology rather than one-off patches.
- Create block level and full chip level PG mesh from scratch using design rule documents, design requirements, and EM/IR feedback.
- Create and maintain a DRC-clean floorplanning flow and enable floorplan signoff checks.
- Drive PPA tuning to optimize tool settings for best power, performance, and area outcomes.
- Establish and maintain timing correlation from pre-route through post-route and between implementation and signoff tools.

You may be a good fit if you have

- 5-10+ years of previous experience with PD or PD methodology/CAD
- Experience building and owning automated RTL-to-GDSII flows used by multiple block owners
- Experience creating block level and full chip level PG mesh from scratch, including interpretation of design rule documents and EM/IR analysis
- Experience with DRC-clean floorplanning flows and automated checks
- Experience with Cadence (Innovus, Genus) or Synopsys ( Fusion Compiler) automated RTL-to-GDSII flows
- Experience with PPA tuning and timing correlation across pre-route, post-route, and signoff environments
- Experience integrating sign-off tools (PrimeTime, Tempus, Voltus, Pegasus, Calibre) into production flows
- Experience with back-end design on advanced process nodes (5nm and below)
- Experience with UPF-based low power design methodology and multi-mode multi-corner setup
- Strong Tcl and Python skills for flow development and automation
- Deeply creative and able to think from first principles

Strong candidates may also have experience with

- Familiarity with modern ML and LLM model architectures
- Familiarity with AI tools for programming/coding
- Experience with compute farm and job scheduler optimization for EDA workloads
- Startup experience or comfort working in fast-paced environments

## Benefits

- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in our office
- Unlimited compute budget subject to ROI justification

## How we’re different

Etched believes in the Bitter Lesson http://www.incompleteideas.net/IncIdeas/BitterLesson.html. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

## About Etched

## Company Overview
- **One-liner**: Etched designs and manufactures specialized ASICs (application-specific integrated circuits) that are hardwired to run transformer-based AI models, offering an order-of-magnitude improvement in inference cost and energy efficiency over general-purpose GPUs.
- **Entity Type**: Private (Series B / later stage; total raised $800M as of June 2026)
- **Headquarters**: San Jose, California, USA (also has offices in Cupertino, CA; Sacramento, CA; and small presence in Taiwan, Canada, UK, Bulgaria)
- **Founded**: 2022
- **Founders**: Gavin Uberti (CEO), Robert Wachen (President & COO), Chris Zhu (Co-Founder)

## Core Business
- **Primary industry**: AI hardware / semiconductor design / computer hardware manufacturing
- **Target customers**: Frontier AI labs, hyperscalers, and enterprises running large-scale transformer inference workloads (B2B, enterprise)
- **Mission / purpose**: Build hardware for superintelligence – specifically, the world’s most powerful servers for transformer inference.

## Products & Services
- **Sohu Chip (ASIC)**: A transformer-specific ASIC manufactured by TSMC. It burns the transformer architecture directly into silicon, eliminating the overhead of general-purpose GPUs for inference.
- **Frontier Inference Clusters**: Full-stack systems that bundle the Sohu chip with custom-designed racks, networking, and software. Customers place orders for complete systems, not just chips. Etched claims they deliver more tokens per dollar and per watt for dense models, sparse MoEs, diffusion models, and more.
- **Software Stack**: Includes compiler and runtime optimizations built by a team with deep experience (former Apache TVM developer, ex-Google TPU software lead).

## Market Standing
- **Valuation**: $5 billion post-money valuation (as of December 2025 / disclosed June 2026)
- **Key Metric**: $1 billion in contract orders (booked) for its systems; total funding of $800M (including an unannounced $500M round closed Dec 2025 led by Stripes)
- **Notable Investors**: Stripes (lead), VentureTech Alliance, Jane Street, Hudson River Trading, Two Sigma, Ribbit Capital. Angel investors include Andrej Karpathy, Geoffrey Hinton, Fei-Fei Li, Arthur Mensch, Scott Wu, Stanley Druckenmiller, Peter Thiel. Earlier backers: Positive Sum, Primary Venture Partners.
- **Growth Signals**:
  - Headcount: 258 employees (as of mid-2026), up 141% year-over-year
  - 100+ active job postings across engineering, operations, and business functions
  - $500M raise in late 2025; first chip manufactured by TSMC in 2025 and now being tested with customers
  - Talent sources include Google (21), Apple (17), NVIDIA (16), Tesla (11), Intel (10), AMD (5)

## Competitive Advantages
- **Transformer-specific architecture**: Unlike GPUs (which are general-purpose), Etched’s chip is hardwired only for transformer operations, enabling drastically lower cost and latency for today’s dominant AI model architecture.
- **Full-stack system play**: By selling entire inference clusters (chip + rack + software), Etched captures more value and delivers a turnkey solution competitive with NVIDIA’s DGX/HGX systems.
- **Deeply experienced leadership**:
  - CEO Gavin Uberti (Harvard math researcher, AI compiler expert, Apache TVM contributor)
  - President Robert Wachen (co-founded Prod AI incubator; Thiel Fellow)
  - VP of Platform (ex-NVIDIA 22 years, built HGX/DGX systems)
  - VP of Software (ex-Google DeepMind, lead TPU v1–v5 software)
  - Chief Architect Saptadeep Pal (former Auradine co-founder, chiplet expert)
  - VP of Hardware Engineering Ajat Hukkoo (ex-Cypress CTO, shipped >$1B revenue products)

## Strategic Focus
- **Scale manufacturing and customer deliveries**: With the first chip successfully fabricated, the company is now testing production systems and aims to fulfill $1B in pre-orders.
- **Expand engineering talent**: Aggressively hiring across silicon design, validation, infrastructure, optics, and software to support volume ramp.
- **Maintain technological lead**: Continue refining the ASIC for future transformer variants and MoE mixtures while building out a partner ecosystem.

## Why Work Here
- **Mission-driven, high-impact engineering**: “Building the hardware for superintelligence” – the company is solving one of the hardest problems in compute (inference efficiency) with a focused team.
- **Top-tier team and learning environment**: Colleagues from Google, NVIDIA, Apple, Tesla, Broadcom, and Intel; exposure to full-stack chip-to-system design.
- **In-office culture**: All roles are in-office (Cupertino and San Jose, CA). The company emphasizes on-site collaboration for hardware development. Notable perks are not heavily advertised, but compensation is competitive for the AI hardware space (equity-heavy).
- **Growth trajectory**: 141% headcount growth YoY, hundreds of open roles, and a $5B valuation signal strong backing and career acceleration potential.
- **Intellectual challenge**: Work on chip simulation, RTL design, system validation, or software infrastructure for cutting-edge AI inference.

## Sources
1. [etched.com/careers](https://www.etched.com/careers)
2. [builtin.com/company/etched](https://builtin.com/company/etched)
3. [linkedin.com/company/etched-ai](https://www.linkedin.com/company/etched-ai)
4. [cbinsights.com/company/etched](https://www.cbinsights.com/company/etched)
5. [techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/](https://techcrunch.com/2026/06/30/nvidia-competitor-etched-hits-5b-valuation-1b-in-sales-for-ai-chip/)

## Other roles at Etched

- [EE Hardware System Engineer (TW)](https://feeny.ai/job/ee-hardware-system-engineer-tw-etched-taipei-fgncym9kzy6w) — Taipei, Taiwan
- [Silicon Validation Engineer, Software](https://feeny.ai/job/silicon-validation-engineer-software-etched-san-jose-qhp3k9xqy5vr) — San Jose, CA
- [RMA & Repair Lead](https://feeny.ai/job/rma-repair-lead-etched-san-jose-q0tmchh0yyrj) — San Jose, CA
- [Advanced Packaging SI/PI Engineer](https://feeny.ai/job/advanced-packaging-si-pi-engineer-etched-san-jose-47he7k0hp901) — San Jose, CA
- [Substrate IC Package Layout Design Engineer](https://feeny.ai/job/substrate-ic-package-layout-design-engineer-etched-san-jose-g36wmxc8ww9r) — San Jose, CA
- [ECAD Librarian](https://feeny.ai/job/ecad-librarian-etched-san-jose-0h5kvj2cxzk4) — San Jose, CA
- [Inventory Warehouse Coordinator](https://feeny.ai/job/inventory-warehouse-coordinator-etched-san-jose-49b0bs49ce57) — San Jose, CA
- [Logistics Analyst (Taiwan)](https://feeny.ai/job/logistics-analyst-taiwan-etched-taipei-5xzc094cqgzn) — Taipei, Taiwan
- [Communications](https://feeny.ai/job/communications-etched-san-jose-3f4bdr97hysp) — San Jose, CA
- [Production Finance](https://feeny.ai/job/production-finance-etched-san-jose-qfypbv9eh0ws) — San Jose, CA