---
title: 'Physical Design / Implementation Lead at Neurophos'
canonical: 'https://feeny.ai/job/physical-design-implementation-lead-neurophos-austin-jge0dfb6md1v'
type: 'job'
last_seen: '2026-09-07'
---

# Physical Design / Implementation Lead at Neurophos

- **Company:** Neurophos
- **Location:** Austin, TX
- **Compensation:** $225k–$300k
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-09-03
- **Last confirmed live:** 2026-09-07
- **Apply:** https://jobs.ashbyhq.com/neurophos/400401dd-b638-4532-b635-858a9671f0a7

## Job description

## ABOUT NEUROPHOS

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A https://www.neurophos.com/110m-raise led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

## POSITION OVERVIEW

We're hiring the first permanent Physical Design / Implementation Lead for the digital design team. This is a build role: you'll be responsible for all aspects of the SoC implementation process. Responsibilities include building and managing a multi-site team to deliver optimized GDSII implementations on subsystem and SoC levels across a variety of planar, FinFet and GAA technologies. You will define how we take designs from RTL to tapeout on leading-edge nodes, and grow the team under you. You'll be one of three discipline leads, alongside RTL and DV, who together own how digital chips get built at Neurophos.

## LOCATION

Austin, TX or San Jose, CA. Full-time onsite position.

## KEY RESPONSIBILITIES

- Own physical design and implementation end-to-end, from synthesis through tapeout, on leading-edge process nodes (TSMC N3 strongly preferred; deep FinFET-class experience, 7nm–3nm, required).
- Optimize and automate our synthesis flow, and lead the intake of new process technology as we bring on new nodes.
- Optimize and automate the timing closure process at the block and subsystem level
- Design and optimization of power and clock architecture distribution networks.
- Own the integration of analog/mixed-signal components into the digital implementation flow, building the process and working relationship between analog and digital teams.
- Own physical verification and IP/library management for the digital design org.
- Build and lead a physical design team: hire, ramp, and manage the engineers under you as the group scales.
- Work closely with the RTL/DV, Analog and other team leads on cross-functional flow and schedule decisions.

## QUALIFICATIONS

- Track record leading physical design / implementation on large, complex SoCs through tapeout: as a back-end lead on a large SoC, or an equivalent composite of synthesis, timing closure, power, and physical-verification ownership at a senior level.
- Hands-on experience on advanced nodes; TSMC N3 strongly preferred, FinFET-class node experience (7nm–3nm) required.
- Deep power and clock design experience at scale, ideally from CPU-class or very large SoC work.
- A track record of leading and growing a team.

## PREFERRED SKILLS

- Experience integrating analog/mixed-signal blocks into a digital implementation flow.
- Cadence toolchain experience.

## WHAT WE OFFER

This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.

## BENEFITS

Join a team that invests in your future and your well-being. At Neurophos, we offer:

- 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
- Unlimited PTO. No rigid vacation banks, just a focus on delivery.
- 401(k) matching and stock option opportunities to ensure our success is your success.
- Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
- Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

## About Neurophos

## Company Overview
- **One-liner**: Neurophos develops photonic AI chips (Optical Processing Units) that perform matrix multiplications at the speed of light, aiming to replace traditional GPUs in data-center inference workloads.
- **Entity Type**: Private, Series A
- **Headquarters**: Austin, Texas, USA (with an additional office in San Jose, California)
- **Founded**: 2020
- **Founders**: Patrick Bowen (CEO, Co-Founder) and Andrew Traverso (Chief Scientist, Co-Founder); other co-founders may include Preston Woo and Hod Finkelstein (CEO, CTO roles indicated on team page).

## Core Business
- **Primary industry**: Semiconductor / Photonic AI Hardware
- **Target customers**: B2B – hyperscale data centers, enterprise AI infrastructure providers
- **Mission/purpose**: “We’re building the first programmable light-speed computer” – solving energy and scalability challenges in AI data centers by using optical rather than electronic computation.

## Products & Services
- **Optical Processing Unit (OPU)**: A photonic AI chip that integrates over one million micron-scale optical processing components on a single die. It performs matrix multiplications in-memory at the speed of light, delivering up to 100x the energy efficiency of traditional GPUs and NVIDIA servers while fitting in a single-GPU form factor. The chip uses an active, programmable metasurface and silicon photonics to achieve 0.47 ExaOPS performance in a 1m x 1m footprint. First systems are targeted for early 2028, with production ramp in mid-2028.

## Market Standing
- **Valuation/Market Cap**: Not disclosed
- **Key Metric**: Total funding raised = **$119.2M** (including a $110M Series A closed in early 2026)
- **Notable Investors**: Gates Frontier (lead), M12 (Microsoft’s venture fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, MetaVC Partners, Gaingels, Mana Ventures, and 22+ others.
- **Growth Signals**: 
  - Recognized on EE Times Silicon 100 list for several consecutive years.
  - Over 300 patents filed and protected.
  - Rapid hiring after Series A – “hypergrowth phase” as per press release.
  - Team includes veterans from NVIDIA, AMD, Apple, Meta, Google, Magic Leap, Micron, Qualcomm, Samsung, and other photonic/AR companies.

## Competitive Advantages
- **Metasurface optical transistors** that are **10,000x smaller** than traditional photonic components, enabling unprecedented density – millions of weights fit in the area of a postage stamp.
- **300+ patents** covering optical metamaterials, neural network accelerators, and machine learning hardware.
- **Energy efficiency**: Up to 100x improvement over existing electronic solutions (e.g., GPUs), directly addressing the power constraints of hyperscale AI inference.
- **Size/performance**: OPU delivers the performance of a 3,000-pound server in the size and power envelope of a single GPU.

## Strategic Focus
- **Commercialization**: First customer evaluations begin in 2026; first OPU systems target early 2028 production ramp.
- **Talent acquisition**: Scaling the team aggressively across analog design, photonics, architecture, and software to meet “hypergrowth” demand.
- **Partnerships**: Leveraging investors like Bosch Ventures (industrial IoT), Aramco Ventures (energy), and M12 (cloud/AI) to align with large-scale data center customers.

## Why Work Here
- **Culture**: In-office, on‑site work culture in Austin, TX (primary) and San Jose, CA. Described as a “world-class team” with leaders from top semiconductor and tech companies.
- **Growth**: Joining at a hypergrowth scale‑up stage with significant funding and a clear path to production; opportunities to shape the architecture and engineering of a new computing paradigm.
- **Engineering focus**: 34 out of 40 total employees are in product + tech roles, indicating a highly technical, R&D-driven environment.
- **Impact**: Work on cutting-edge optical computing that could redefine AI hardware efficiency; involvement in everything from silicon photonics to compiler software.
- **Notable perks**: Not explicitly listed, but being a well-funded deep-tech startup likely offers competitive equity, technical challenges, and direct mentorship from industry veterans.

## Sources
1. [neurophos.com](https://www.neurophos.com/)
2. [neurophos.com/careers](https://www.neurophos.com/careers)
3. [neurophos.com/team](https://www.neurophos.com/team)
4. [cbinsights.com](https://www.cbinsights.com/company/neurophos)
5. [builtin.com](https://builtin.com/company/neurophos)

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