---
title: 'Physical Design - SOC Top Lead at Efficient Computer'
canonical: 'https://feeny.ai/job/physical-design-soc-top-lead-efficient-computer-san-jose-ca-or-pittsburgh-pa-or-pffdcqd79zpv'
type: 'job'
last_seen: '2026-09-10'
---

# Physical Design - SOC Top Lead at Efficient Computer

- **Company:** Efficient Computer
- **Location:** San Jose CA OR Pittsburgh PA OR Austin, TX
- **Posted:** 2026-08-04
- **Last confirmed live:** 2026-09-10
- **Apply:** https://job-boards.greenhouse.io/efficientcomputer/jobs/4343792009

## Job description

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

We're looking for a Lead Physical Design Engineer to take end-to-end ownership of SOC -top for our next-generation SoCs. This is a hands-on, high-accountability role — you'll be the single point of ownership driving the full chip from block integration through timing, power, signal integrity, and physical closure to tapeout-ready GDS. You'll work closely with block-level PD owners, DFT, package/IO teams, and the architecture team. This role will be in the newly formed hardware engineering group and will focus on designing in state of the art finfet technologies.

This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

## Key Responsibilities

- Full-chip integration: floorplanning, power planning, macro/hard-IP placement, and block partitioning at the top level, ensuring convergence across all hierarchical blocks
- Timing closure: full-chip STA across all corners/modes (setup, hold, OCV, multi-mode multi-corner), including cross-boundary timing and chip-level constraint (SDC) ownership
- Power: full-chip power planning, PDN design/analysis (IR drop, EM), rail architecture, and coordination on power-gating strategy with block owners
- Physical verification: DRC/LVS/antenna closure at the top level, seal ring integration, and coordination of ECO cycles across blocks
- Signal integrity & noise: crosstalk, di/dt, and chip-level noise closure, especially around high-speed IO and PLL/analog boundaries
- Clock & reset architecture: top-level clock tree strategy across domains, including CTS coordination with block owners
- DFT integration: chip-level scan stitching, MBIST/JTAG integration, and coordination with DFT lead on ATPG/test coverage closure at full-chip level
- Package/IO co-design: bump/ball map coordination, IO ring planning, and package-aware floorplanning
- Tapeout readiness: sign-off checklist ownership (timing, power, physical, reliability) and final GDS handoff
- Cross-team coordination: single point of contact between block-level PD owners, DV, DFT, package engineering, and architecture on all convergence-related tradeoffs and schedule risk
- Technical leadership: mentor block-level PD engineers on convergence best practices; set methodology and flow standards for chip-top closure across the program.

Required Qualifications

- Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
- 8-12+ years of physical design experience, with at least 2-3 full tapeouts at the chip-top/SoC integration level (not just block-level)
- Deep hands-on experience with advanced nodes
- Proven track record owning full-chip timing closure across multiple corners/modes on a complex SoC
- Strong PDN/IR-drop/EM analysis experience (Voltus or equivalent)
- Experience with chip-level DFT integration (scan stitching, MBIST, JTAG)
- Familiarity with package co-design (flip-chip/BGA, C4 bumps, ball map) is a plus
- Tool fluency: Innovus (or ICC2), Tempus/PrimeTime, RedHawk, Calibre
- Demonstrated ability to lead technically without direct reports — driving alignment across multiple engineers and teams on convergence decisions
- Comfortable operating with significant ownership and ambiguity in a small, fast-moving team — this isn't a role where you hand off convergence problems, you solve them
- Experience with non-standard/novel architectures (dataflow, tiled, NoC-based) is a plus but not required
- Excellent scripting skills in TCL, shell and python.

Desired Qualifications & Experience Requirements

- Knowledge of computer architecture
- Knowledge of physical design and ASIC implementation
- Experience in full chip sign off convergence
- Knowledge of circuit design, device physics, deep sub-micron technology and its implications to physical design
- Proficiency with industry-grade physical design flow.
- Experience in integrating analog or mixed-signal macro on top-level design.

We offer a competitive salary for this role, generally ranging from $200,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate. Why Join Efficient?

Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.

## About Efficient Computer

## Company Overview
- **One-liner**: Efficient Computer is building the world’s most energy-efficient general-purpose processor by combining a novel Fabric architecture with an intuitive compiler, targeting edge AI, industrial automation, space/defense, and beyond.
- **Entity Type**: Private (Series A)
- **Headquarters**: Pittsburgh, Pennsylvania, United States
- **Founded**: 2022
- **Founders**: Brandon Lucia (CEO) and Nathan Beckmann (Chief Architect)

## Core Business
- Primary industry/industries: Semiconductor / Computer Hardware / AI Chips
- Target customers: B2B – OEMs and systems integrators in edge AI, industrial automation, satellite/space, automotive, defense, and consumer electronics
- Mission or purpose statement: To set a new standard for energy efficiency in general-purpose computation, enabling applications that are infeasible today due to energy constraints. [efficient.computer/about](https://www.efficient.computer/about)

## Products & Services
- **[Electron E1 Processor]**: A general-purpose processor featuring the proprietary Fabric architecture and 4MB of on-chip MRAM. It replaces von Neumann execution with a spatial dataflow model, delivering up to 1 TOPS/W and scaling from 5.4 GOPS to 21.6 GOPS. Designed for always-on AI inference at the edge. [efficient.computer/technology](https://www.efficient.computer/technology)
- **[effcc Compiler]**: A drop-in replacement for GCC/Clang that automatically extracts parallelism from C, C++, and TFLite code and maps it to the Fabric architecture. Provides ultra-fast compilation times and a GDB-compatible debugging experience. [efficient.computer/technology](https://www.efficient.computer/technology)
- **[Fabric Architecture]**: The core technology – a tiled grid of reconfigurable compute nodes that eliminates instruction fetch and decode overhead, achieving 10–100× energy efficiency gains over traditional CPUs and GPUs. [efficient.computer](https://www.efficient.computer/)

## Market Standing
- **Valuation/Market Cap**: Not disclosed (private company)
- **Key Metric**: Total Funding – $70.0M across 3 rounds (Seed and Series A)
- **Notable Investors/Partners**: Triatomic Capital (led Series A), Eclipse (led Seed round). Key advisors include Alex Hawkinson (founder of SmartThings and BrightAI). [linkedin.com/company/efficientcomputer](https://www.linkedin.com/company/efficientcomputer)
- **Growth Signals**: 
  - 46 employees (+79.4% YoY, +27 people)
  - 13,966 LinkedIn followers (+180.4% yearly growth)
  - First silicon product (Electron E1) delivered to customers in mid-2025, ramping to volume distribution in 2026
  - Customer traction in physical AI, space/defense, automotive, and consumer products

## Competitive Advantages
- **Fabric Architecture**: A fundamentally new compute paradigm that is 10–100× more energy-efficient than traditional CPUs/GPUs for general-purpose workloads, including AI inference.
- **Full Programmability**: Unlike specialized accelerators that only optimize isolated kernels, the Fabric architecture accelerates entire applications without requiring code rewrites.
- **Proven Silicon**: Two silicon implementations (Electron E0 prototype and Electron E1 product) are already in customer hands.
- **World-Class Team**: Founders and key engineers are leading computer architects from Carnegie Mellon University, with deep expertise in efficient computing.

## Strategic Focus
- Scale the Electron E1 processor into high-volume production and distribution (targeting 2026).
- Expand into multiple verticals: physical AI, industrial automation, space/satellite, defense, automotive, and consumer electronics.
- Continue developing the effcc compiler ecosystem to support more frameworks and languages.
- Grow the engineering team, particularly in physical design, verification, architecture, and software optimization.

## Why Work Here
- **Cutting-Edge Technology**: Work on a novel processor architecture that redefines energy efficiency for the AI era.
- **Strong Growth Trajectory**: The company is scaling rapidly (nearly 80% headcount growth YoY) with a clear product-market fit and customer traction.
- **Engineering-Centric Culture**: 43% of the workforce is in technical roles, with a focus on computer architecture, compiler design, and silicon engineering.
- **Compensation & Benefits**: Competitive base salaries, meaningful startup equity, 401k matching, and a choose-your-own-adventure equipment allowance. [efficient.computer/about](https://www.efficient.computer/about)
- **Work Locations**: Offices in Pittsburgh, PA; San Jose, CA; and Austin, TX. Roles are on-site/hybrid at these hubs.
- **Values-Driven**: The company emphasizes integrity, impact, and accountability. [efficient.computer/about](https://www.efficient.computer/about)
- **Open Roles (as of mid-2026)**: 7 active positions including Design Verification Manager, Hardware Infrastructure & CI/CD Engineer, Senior Product Managers (Hardware/Software), Computer Architect, and Lead Physical Design Engineer.

## Sources
1. [efficient.computer](https://www.efficient.computer/)
2. [efficient.computer/about](https://www.efficient.computer/about)
3. [efficient.computer/technology](https://www.efficient.computer/technology)
4. [linkedin.com/company/efficientcomputer](https://www.linkedin.com/company/efficientcomputer)
5. [job-boards.greenhouse.io/efficientcomputer](http://job-boards.greenhouse.io/efficientcomputer)

## Other roles at Efficient Computer

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- [Senior Digital Verification Engineer](https://feeny.ai/job/senior-digital-verification-engineer-efficient-computer-san-jose-ca-or-gbtgaqxktxcn) — San Jose CA OR Pittsburgh PA OR Austin, TX
- [Senior Embedded Engineer](https://feeny.ai/job/senior-embedded-engineer-efficient-computer-san-jose-ca-or-pittsburgh-wap31cd60m1c) — San Jose CA OR Pittsburgh, PA
- [Applications Engineer - Silicon IP](https://feeny.ai/job/applications-engineer-silicon-ip-efficient-computer-san-jose-ca-or-pittsburgh-c1tv4xa629w9) — San Jose CA OR Pittsburgh PA OR Austin, TX
- [Computer Architect](https://feeny.ai/job/computer-architect-efficient-computer-pittsburgh-pa-san-jose-ca-austin-0bq0yc0jre5d) — Pittsburgh PA San Jose CA Austin, TX
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- [Test Engineer](https://feeny.ai/job/test-engineer-efficient-computer-san-jose-t9qqz05wbzee) — San Jose, CA
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