---
title: 'Physical Verification Engineer (Staff / Sr. Staff) at Velaura'
canonical: 'https://feeny.ai/job/physical-verification-engineer-staff-sr-staff-velaura-bengaluru-4k6ypqtyjv23'
type: 'job'
last_seen: '2026-09-11'
---

# Physical Verification Engineer (Staff / Sr. Staff) at Velaura

- **Company:** Velaura
- **Location:** Bengaluru, India
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-08-18
- **Last confirmed live:** 2026-09-11
- **Apply:** https://jobs.lever.co/velaura/ce07af94-e792-4bd0-ae1a-3baf342259a2

## Job description

## Role Overview

As a Staff/Sr. Staff Physical Verification Engineer at Velaura AI, you will own block-level and full-chip physical verification and signoff for next-generation AI and high-performance computing silicon. You will drive physical verification from block-level implementation through full-chip integration and final tape-out, working on complex SoC designs targeting advanced process technologies. This is a highly hands-on technical role requiring deep expertise in DRC, LVS, ERC, PERC, antenna, ESD/EOS, and reliability verification, along with the ability to identify root causes and implement physical fixes directly in Cadence Innovus and/or Synopsys Fusion Compiler. You will work closely with Physical Design, Analog/Mixed-Signal, STA, Power Integrity, Reliability, I/O, and CAD teams to drive signoff convergence, establish robust PV methodologies, and achieve first-time-right silicon.

## Responsibilities

● Own block-level and full-chip physical verification signoff, including DRC, LVS, ERC, PERC, antenna, ESD/EOS, and related reliability checks for complex ASIC/SoC designs.

● Drive tape-out readiness and signoff closure through violation triage, root-cause analysis, waiver management, schedule tracking, and convergence to zero or signoff-acceptable violations.

● Execute and debug physical verification using industry-standard tools such as Siemens Calibre and Synopsys IC Validator (ICV), including complex connectivity, device-recognition, hierarchy, and advanced-node rule issues.

● Correlate Calibre/ICV results with Cadence Innovus and/or Synopsys Fusion Compiler implementation databases and drive physical fixes through iterative verification to closure.

● Perform hands-on physical implementation and ECO changes, including routing and via edits, metal-shape modifications, cell movement, filler/decap/endcap updates, power-grid modifications, and other layout changes required for signoff.

● Define, customize, and enhance PERC and reliability verification flows covering ESD, EOS, latch-up, point-to-point resistance, current-density constraints, and high-current paths.

● Develop Tcl and Python/Perl/Unix shell automation for violation analysis, implementation database queries, physical ECOs, PV execution, and signoff reporting.

● Drive PV closure for advanced FinFET and GAA technologies, including restrictive spacing, coloring, cut-mask, EUV/multi-patterning, and other advanced-node-specific requirements.

● Influence floorplanning, power-grid planning, and implementation methodology from a physical verification perspective to minimize downstream iterations and late-stage signoff violations.

● Support hierarchical and full-chip PV methodologies for digital-on-top, mixed-signal, and multi-voltage SoCs, including IP integration and boundary/interface verification.

● Partner with Physical Design, STA, Power Integrity, Analog, and Reliability teams to ensure PV-driven changes preserve timing, congestion, routability, signal integrity, power integrity, reliability, and design functionality.

● Develop and optimize physical verification flows for runtime, scalability, robustness, and ease of use across block and full-chip designs.

● Partner with CAD teams, foundries, and EDA vendors to qualify technology nodes and rule decks, resolve complex PV/reliability issues, and improve verification and signoff methodologies.

● Drive density, metal-fill, DFM/DFY, and pattern-matching verification while ensuring associated changes do not introduce timing, reliability, or physical verification regressions.

● Mentor engineers on physical verification methodology, advanced-node debugging, root-cause analysis, implementation fixes, and tape-out signoff best practices.

Required Qualifications

● Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related field.

● Typically 8+ years of relevant experience in physical verification for complex ASIC/SoC designs, with multiple successful production tape-outs.

● Proven experience owning block-level and/or full-chip physical verification signoff for complex ASIC/SoC designs.

● Strong hands-on experience with DRC and LVS signoff, with experience or strong exposure to PERC and reliability verification.

● Experience with advanced FinFET and/or GAA technologies, including at least one production tape-out at an advanced process node.

● Strong hands-on expertise with Siemens Calibre and/or Synopsys ICV, including debugging complex DRC, LVS, antenna, connectivity, and advanced-node physical verification issues.

● Demonstrated ability to perform manual and scripted physical implementation/ECO changes in Cadence Innovus and/or Synopsys Fusion Compiler.

● Experience correlating physical verification results with implementation databases and driving physical fixes through iterative verification to signoff closure.

● Strong scripting skills in Tcl and at least one of Python, Perl, or Unix shell for PV automation, implementation database queries, ECOs, and flow development.

● Strong understanding of how PV-driven physical changes impact timing, congestion, routability, signal integrity, power integrity, reliability, and overall design closure.

● Strong debugging, problem-solving, and root-cause-analysis skills, with the ability to independently drive complex signoff issues to closure.

● Excellent communication skills and the ability to work effectively across Physical Design, Analog, STA, CAD, Reliability, Foundry, and EDA teams.

## Preferred Qualifications

● Hands-on experience with PERC-based reliability verification for ESD, EOS, latch-up, point-to-point resistance, current-density constraints, and high-current paths, including flow setup, customization, debugging, and definition of signoff criteria.

● Experience with Cadence Virtuoso integration with Calibre/ICV for DRC, LVS, and PERC verification in analog or mixed-signal environments.

● Experience driving hierarchical and full-chip PV signoff for digital-on-top, mixed-signal, and/or multi-voltage SoCs.

● Experience with DFM/DFY, density and metal-fill strategies, pattern-matching verification, and advanced-node manufacturing checks.

● Experience qualifying foundry rule decks, new technology nodes, verification methodologies, and signoff flows.

● Experience working directly with foundries and EDA vendors on complex rule interpretation, deck, methodology, and signoff issues.

● Experience working in a fast-paced or early-stage semiconductor environment.

Why Velaura? Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world. This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

## Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans. Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: careers@velaura.ai. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

## About Velaura

## Company Overview
- **One-liner**: Velaura (formerly Auradine) is a semiconductor and systems company building ultra-low-power compute infrastructure for AI workloads across cloud, edge, and physical AI applications.
- **Entity Type**: Private (Series C, $314M total funding)
- **Headquarters**: Santa Clara, California, USA
- **Founded**: 2023 (as Auradine; rebranded to Velaura AI in 2026)
- **Founders**: Co-founded by Rajiv Khemani (CEO), YJ Kim (President, Products), Sanjay Gupta (President, Strategy & GTM), and Manu Gulati (Chief Development Officer)

## Core Business
- **Primary Industry**: Semiconductor design, AI compute infrastructure, ultra-low-power ASICs
- **Target Customers**: Hyperscale data centers, AI/ML platform providers, edge computing companies, and physical AI (robotics, automotive) OEMs — primarily **B2B Enterprise**
- **Mission**: To deliver proven, breakthrough, ultra-low-power compute for cloud, edge, and physical AI applications, solving the power bottleneck that constrains AI scaling.

## Products & Services
- **Proprietary Ultra-Low-Power Digital Design Technology**: Patented IP and toolflow that reduces power consumption of arithmetic operations by 2–4x on leading process nodes, translating to ~$650–$1,300/chip in power savings over 3 years. Output is optimized GDS or chiplets.
- **Custom AI Accelerators (ASICs)**: Full-custom silicon solutions for AI inference and training workloads, co-designed with customers (RTL input → optimized GDS).
- **Engagement Model**: Customer provides RTL design and priorities; Velaura applies its proprietary methodology, low-voltage libraries, and custom circuit expertise to deliver power-optimized chip designs with proven yield and reliability.

## Market Standing
- **Valuation/Market Cap**: Not publicly disclosed (private company)
- **Key Metric**: **$314M total funding** across 4 rounds
  - Series A (2023): $71M from 6 investors
  - Debt Financing (2023): $10M
  - Series B (2024): $80M from 7 investors
  - Series C (2025): $153M from 8 investors
- **Notable Investors/Partners**: Backed by top-tier VCs (specific names not publicly listed; investors include firms with deep semiconductor expertise) — talent sources include Qualcomm, Arm, Apple, Google, NVIDIA, Intel, Palo Alto Networks, Stripe
- **Growth Signals**:
  - Rebranded from Auradine to Velaura AI in August 2026, signaling strategic expansion into AI compute
  - Added Manu Gulati (ex-NUVIA co-founder, Apple/Google silicon architect) as Co-founder & Chief Development Officer
  - Added Aditya Grover (Co-founder & CTO of Inception, Stanford PhD, part of the team that invented Diffusion models) as Founding Advisor
  - Workforce of 42 employees growing at +4.3% monthly; headcount split ~47% US / 39% India
  - Offices in Santa Clara, CA (HQ) and additional US location, with hiring across hardware and software engineering in Bangalore, Austin, and Boston

## Competitive Advantages
- **Patented ultra-low-power digital design technology** field-proven over multiple years across tens of millions of ASICs deployed with world-class yield and reliability
- **Founding team with exceptional pedigree**: seasoned entrepreneurs and technologists from Qualcomm, Marvell, NVIDIA, Intel, Palo Alto Networks, Apple, Google, and NUVIA (acquired by Qualcomm for ~$1.5B)
- **Systems-level thinking**: combines deep silicon expertise with AI/ML domain knowledge to tackle power as the primary bottleneck for AI at scale
- **Engagement model** that allows customers to leverage Velaura’s IP without fully outsourcing chip design — outputs optimized GDS or chiplets on latest process nodes

## Strategic Focus
- **Scale ultra-low-power compute across three domains**: cloud data centers, edge/enterprise, and physical AI (robotics, autonomous systems)
- **Hire aggressively** for engineering leadership: compiler development, platform software, CAD/methodology, RTL, design verification, advanced packaging, AI architecture, and hardware/software co-design
- **Productize its proprietary IP** into standard offerings for hyperscalers and AI chip companies
- **Continue raising capital** (largest round was $153M Series C in April 2025) to fund expansion

## Why Work Here
- **Culture**: Deep engineering DNA and systems-level thinking — the team is solving one of AI’s hardest physical constraints (power) with proven silicon technology
- **Growth trajectory**: Rapidly scaling startup (42 employees, +4.3% monthly headcount growth, $314M raised) with a clear path to becoming a key infrastructure provider for the AI era
- **Leadership**: Led by industry veterans (NUVIA, Apple, Google, Qualcomm) who have built billion-dollar silicon companies and products powering billions of devices
- **Work environment**: On-site roles in Santa Clara, CA; Austin, Texas; and Bangalore, India. Remote/hybrid policy not specified but multiple office locations suggest flexible collaboration.
- **Impact**: Opportunity to work on cutting-edge AI hardware design, from architecture through tape-out and deployment, with direct impact on the power efficiency of the world’s largest AI clusters
- **Notable perks**: Not publicly detailed, but the company’s focus on high-end engineering talent suggests competitive compensation, equity, and exposure to top-tier semiconductor and AI technology

## Sources
1. [velaura.ai](https://velaura.ai/introducing-velaura-ai/)
2. [velaura.ai](https://velaura.ai/team/)
3. [velaura.ai](https://velaura.ai/low-power-ai-compute/)
4. [jobs.lever.co/velaura](https://jobs.lever.co/velaura/)
5. [linkedin.com](https://linkedin.com/company/velaura-ai-inc)
6. [wellfound.com](https://wellfound.com/company/velaura-ai) (Apollo data extracted on financials and headcount)

SUGGESTED_INDUSTRY: semiconductor-manufacturing-robotics-ai-infrastructure
_(Note: The above slug is not in the provided list. Closest match from the list is `artificial-intelligence`. However, given the company's core business is semiconductor design and power-efficient AI compute infrastructure, `manufacturing-robotics` or `infrastructure` also fit. For strict adherence to the provided list: `artificial-intelligence` is the best single choice.)_

## Other roles at Velaura

- [Office Admin / Receptionist](https://feeny.ai/job/office-admin-receptionist-velaura-santa-clara-asc5tq6ff9ze) — Santa Clara, CA
- [Sr Engineer CAD Pre-Silicon Front End](https://feeny.ai/job/sr-engineer-cad-pre-silicon-front-end-velaura-santa-clara-91g66vhzqqt3) — Santa Clara, CA
- [Director of IT Infrastructure & Operations](https://feeny.ai/job/director-of-it-infrastructure-operations-velaura-santa-clara-46t1yb690v9g) — Santa Clara, CA
- [RTL Power Engineer](https://feeny.ai/job/rtl-power-engineer-velaura-santa-clara-jyj4n03rckrf) — Santa Clara, CA
- [Design Verification Engineer- AI Accelerator](https://feeny.ai/job/design-verification-engineer-ai-accelerator-velaura-santa-clara-15tk23smaz5x) — Santa Clara, CA
- [Design Verification Engineer- CPU](https://feeny.ai/job/design-verification-engineer-cpu-velaura-santa-clara-d1bkx2h2dj9g) — Santa Clara, CA
- [CAD & Engineering Infrastructure Lead](https://feeny.ai/job/cad-engineering-infrastructure-lead-velaura-santa-clara-eca75sba2s9n) — Santa Clara, CA
- [Senior Technical Recruiter – Engineering](https://feeny.ai/job/senior-technical-recruiter-engineering-velaura-santa-clara-v66mv6d4ghqd) — Santa Clara, CA
- [Principal AI SoC Runtime Software Architect](https://feeny.ai/job/principal-ai-soc-runtime-software-architect-velaura-santa-clara-bf6ceyep3azn) — Santa Clara, CA
- [Senior Engineering Program Manager](https://feeny.ai/job/senior-engineering-program-manager-velaura-santa-clara-73yycn9ge0f3) — Santa Clara, CA