---
title: 'Post-Silicon Validation Engineer (Multiple Levels) at Celero Communications, Inc.'
canonical: 'https://feeny.ai/job/post-silicon-validation-engineer-multiple-levels-celero-communications-inc-wrpm0f2vanb5'
type: 'job'
last_seen: '2026-11-06'
---

# Post-Silicon Validation Engineer (Multiple Levels) at Celero Communications, Inc.

- **Company:** Celero Communications, Inc.
- **Location:** Irvine CA OR Ottawa Ontario, Canada
- **Posted:** 2026-10-21
- **Last confirmed live:** 2026-11-06
- **Apply:** https://job-boards.greenhouse.io/celerocommunicationsinc/jobs/4458440009

## Job description

## About The Role

Celero is seeking  Post-Silicon Validation Engineers to join our validation team for next-generation coherent DSP ASICs powering AI and hyperscale optical networking. As a member of our engineering team, you will play an important role in enabling first silicon, silicon characterization, and ensuring product readiness for customer deployment and high-volume production.

We are seeking multiple levels from early career to Senior Staff level.

This is a role within a fast-paced startup where you will work with Architecture, Design, Firmware, Systems, Apps, Marketing, ATE, Product Engineering, and customers to solve complex silicon challenges. You will have the opportunity to participate in validation strategy, shape best practices, and be a part of our validation infrastructure from the ground up.

## What You'll Do

- Post-silicon validation and characterization of complex ASICs and SoCs from first silicon through production release
- Participate in functionality, performance, interoperability, compliance, stress testing, corner cases, and reliability functions
- Enable first silicon bring-up using JTAG, scan, embedded debug features, and board-level diagnostics
- Validate high-speed interfaces including PCIe, Ethernet, SerDes and other industry-standard protocols
- Utilize advanced lab equipment including high-bandwidth oscilloscopes, BERTs, protocol analyzers, Ethernet traffic generators, network analyzers, logic analyzers, and power measurement equipment
- Debug complex hardware, firmware, RTL, and system-level issues while working closely with cross-functional engineering teams to identify root causes and drive timely resolution
- Contribute to scalable Python-based automation frameworks for test execution, regression, silicon characterization, data analysis, and reporting
- Validate firmware, bootloaders, device drivers, and hardware/software interfaces across multiple platforms
- Characterize silicon performance, power, thermal behavior, margins, and compliance against architectural specifications
- Participate in debug reviews and technical direction for validation methodology, infrastructure, and best practices
- Support early customer engagements by reproducing and resolving system-level issues and collaborating with applications engineering
- Document validation results, silicon characterization data, debug findings, and production readiness reports

## What You'll Bring

## Basic Qualifications

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent experience in lieu of formal education
- Hands-on post-silicon validation, DVT, or silicon bring-up experience with complex ASICs or SoCs
- Understanding of silicon debug methodologies and structured root-cause analysis
- Knowledge of one or more high-speed protocols including PCIe, Ethernet, SerDes, CXL, USB, SPI, I²C, or similar interfaces
- Python programming skills for automation, regression development, and data analysis
- Excellent communication skills with the ability to work effectively across cross-functional teams
- Comfortable working in a fast-paced startup environment where priorities evolve quickly and every team member has significant technical ownership
- Ability to work onsite full-time at our Irvine, California or Ottawa, Canada headquarters. This is not a remote position. We will provide relocation for qualified candidates.
- Ability to interpret schematics, understand board design, power sequencing, signal integrity, and hardware debug

## Preferred Qualifications

- Experience bringing first silicon to production in networking, communications, data center, AI, or high-performance computing products.
- Experience using laboratory equipment including oscilloscopes, BERTs, protocol analyzers, network analyzers, logic analyzers, and related validaton tools
- Experience validating firmware, embedded software, drivers, and hardware/software interfaces
- Experience validating coherent optical DSPs, networking ASICs, Ethernet switch silicon, AI accelerators, GPUs, storage controllers, or high-speed communications devices
- Strong knowledge of Ethernet, PCIe, OIF, IEEE, or related compliance specifications
- Experience building scalable validation automation, regression systems, dashboards, and data pipelines
- Familiarity with customer platform validation and hyperscale qualification processes

Annual Base Salary Range for US: $100,000 - $200,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

## About Celero Communications, Inc.

## Company Overview
- **One-liner**: Celero Communications develops advanced coherent DSP solutions that enable high-bandwidth, low-power optical connectivity for AI infrastructure, eliminating distance bottlenecks in data centers.
- **Entity Type**: Private (Series B; total funding $148.4M per LinkedIn, $140M per company press release)
- **Headquarters**: Irvine, California, USA
- **Founded**: 2024
- **Founders**: Nariman Yousefi (CEO, President & Co-founder) and Oscar Agazzi (CTO & Co-founder)

## Core Business
- **Primary industry**: Semiconductor manufacturing / optical networking for AI infrastructure
- **Target customers**: B2B – hyperscale data centers, AI cloud providers, and large-scale accelerated computing clusters
- **Mission**: “Deliver the optical performance and scalability needed for the next generation of accelerated computing” [celero.inc](https://celero.inc/about/)

## Products & Services
- **Coherent DSP Platform**: A digital signal processor that provides light-speed performance, bandwidth efficiency, and scalable optical links for AI accelerators, servers, and clusters. The technology is described as 100x more efficient than conventional optical transmission and is designed for interoperability across diverse AI and cloud platforms. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/)

## Market Standing
- **Valuation**: Not publicly disclosed
- **Key Metric**: Total funding of **$148.4 million** (Seed $8.4M led by Sutter Hill Ventures; Venture Round $40M; Series B $100M led by CapitalG) [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Notable Investors/Partners**: Sutter Hill Ventures (lead seed & Series A), CapitalG (lead Series B), plus other undisclosed investors in venture round [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Growth Signals**: Founded in 2024, already employs **93 people** with a monthly headcount growth of **+9.3%**. Operates design centers in Irvine (CA), Ottawa (Canada), and Córdoba (Argentina). [linkedin.com](https://www.linkedin.com/company/celero-communications)

## Competitive Advantages
- **Founding team** consists of industry pioneers from Marvell, Inphi, Broadcom, and ClariPhy with decades of experience in analog design, digital signal processing, and optical networking. [celero.inc](https://celero.inc/about/)
- **Coherent DSP technology** that eliminates distance bottlenecks, delivering 100x more efficient optical transmission for scale-across AI infrastructure. [celero.inc](https://celero.inc/)
- **System flexibility and interoperability** across diverse AI and cloud platforms, making it easier for data centers to adopt. [celero.inc](https://celero.inc/)

## Strategic Focus
- **Current priorities**: Scaling AI infrastructure connectivity by delivering high-bandwidth, low-power optical links; expanding engineering teams across all design centers; and building energy-efficient systems that redefine how data centers connect. [celero.inc](https://celero.inc/careers/)

## Why Work Here
- **Culture**: Described as driven by curiosity, precision, and the challenge of making AI systems faster and more energy-efficient. Employees collaborate with global experts in coherent DSP and optical engineering. [celero.inc](https://celero.inc/careers/)
- **Work model**: On-site/hybrid at three locations – Irvine, CA (HQ); Ottawa, Canada; and Córdoba, Argentina. Multiple engineering roles (Analog Design, ASIC, DSP, Firmware, Verification) are posted with specific location requirements. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc)
- **Notable perks**: Opportunity to work on next-generation AI infrastructure technology alongside industry pioneers. The company emphasizes building scalable, energy-efficient systems and offers roles across R&D, operations, and manufacturing. [celero.inc](https://celero.inc/careers/)

## Sources
1. [celero.inc](https://celero.inc/) – Company homepage and product description
2. [celero.inc](https://celero.inc/about/) – About page (founding, leadership, mission)
3. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/) – Press release on $140M funding
4. [linkedin.com](https://www.linkedin.com/company/celero-communications) – LinkedIn company page (funding details, headcount, locations, employee breakdown)
5. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc) – Careers page (open positions, locations)

## Other roles at Celero Communications, Inc.

- [Office Manager](https://feeny.ai/job/office-manager-celero-communications-inc-san-jose-cn78s1p95vfp) — San Jose, CA
- [Junior Emulation Engineer](https://feeny.ai/job/junior-emulation-engineer-celero-communications-inc-cordoba-mr1rgy0be981) — Cordoba, Argentina
- [Senior ASIC Design Engineer - DSP/Analog/SerDes](https://feeny.ai/job/senior-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-ottawa-x63zcvwcjacj) — Ottawa, Canada
- [Senior ASIC Design Engineer - DSP/Analog/SerDes](https://feeny.ai/job/senior-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-irvine-cetabymy86nx) — Irvine, CA
- [Senior ASIC Design Engineer - DSP/Analog/SerDes](https://feeny.ai/job/senior-asic-design-engineer-dsp-analog-serdes-celero-communications-inc-san-jose-aybnp6fps5vc) — San Jose, CA
- [Principal Optical Systems Engineer](https://feeny.ai/job/principal-optical-systems-engineer-celero-communications-inc-ottawa-5esg1r55angb) — Ottawa, Canada
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-abktjq9g2jgw) — Ottawa, Canada
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-4kasvranjrvf) — San Jose, CA
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-vnzcs82knnj6) — Irvine, CA
- [High-Speed Analog Layout Design Engineer](https://feeny.ai/job/high-speed-analog-layout-design-engineer-celero-communications-inc-cordoba-k9yg56pm5h0s) — Córdoba, Argentina