---
title: 'Power Architect – AI SOC at EnCharge AI'
canonical: 'https://feeny.ai/job/power-architect-ai-soc-encharge-ai-india-0wp4dnqt2nfc'
type: 'job'
last_seen: '2026-10-24'
---

# Power Architect – AI SOC at EnCharge AI

- **Company:** EnCharge AI
- **Location:** India
- **Posted:** 2026-10-20
- **Last confirmed live:** 2026-10-24
- **Apply:** https://job-boards.greenhouse.io/enchargeai36/jobs/4460060009

## Job description

Power Architect – AI SOC

Location: Bangalore Hybrid/ Remote

## About EnCharge AI

EnCharge AI is building the next generation AI platform. Our novel in-memory-computing architecture delivers a 10x step-function improvement in compute energy efficiency and performance for AI inference workloads. As the demands of artificial intelligence move beyond today's models, we believe fundamental underlying infrastructure must evolve. We are an experienced team of AI researchers, silicon & systems engineers, and architects backed by leading investors, poised to become the essential platform for the next wave of AI innovation.

Role Overview:

We are seeking a critical-thinking, highly collaborative Power Architect to drive end-to-end PPA (Power, Performance, Area) excellence for our next-generation AI semiconductor chips. In this cross-functional IC role, you will bridge the gap between front-end conceptualization and back-end implementation, influencing SoC architecture, RTL design, and physical layout to deliver industry-leading power efficiency for complex AI workloads.

Key Responsibilities:

- Architectural Influence: Drive comprehensive SoC-level power and thermal management architecture. Influence microarchitecture, memory hierarchies, and dataflows to minimize dynamic and leakage power for AI inference and training workloads.
- RTL & Floorplan Guidance: Review and guide RTL implementation to ensure consistency with power and timing goals. Collaborate directly with Physical Design (PD) teams to refine area constraints, floorplanning, and multi-voltage domain structures.
- PD Recipe Engineering: Develop, fine-tune, and build advanced Physical Design recipes (covering synthesis, placement, clock tree synthesis, and routing) specifically tailored to achieve best-in-class PPA targets.
- EDA & Custom Solutions: Partner with EDA vendors and internal teams to drive the adoption and customization of advanced power analysis tools (e.g., PowerArtist, PrimePower, Joules). Develop custom scripts and design workflows where standard tools fall short to squeeze out every milliwatt of power savings.
- Cross-Functional Collaboration: Lead PPA analysis and trade-off discussions across RTL, architecture, and PD teams. Act as the central hub to resolve complex bottlenecks and ensure the final silicon meets strict power budgets.

Who You Are:

- A Critical Thinker: You look beyond block-level metrics to understand how early architectural choices impact the final silicon's physical layout and thermal limits.
- A Master Collaborator: You excel at breaking down silos, bringing together hardware, physical design, and software/firmware teams to achieve a unified PPA goal.
- An Innovator: You aren't satisfied with default EDA flows and actively build custom methodologies to push the boundaries of chip efficiency.

Qualifications:

- BS/MS/PhD in Electrical Engineering, Computer Engineering, or a related field.
- 12+ years of semiconductor experience with a deep focus on SoC architecture, low-power RTL design, and Physical Design (PD) implementation.
- Proven track record of delivering complex, high-performance silicon (AI accelerators, GPUs, or advanced SoCs) under stringent PPA constraints.
- Hands-on expertise with power intent (UPF/CPF) and industry-standard power estimation/analysis tools.
- Strong scripting and automation skills (Python, Tcl, Perl) for customizing EDA tool flows and PPA data analysis.

## About EnCharge AI

## Company Overview
- **One-liner**: EnCharge AI develops analog in-memory computing hardware and software to deliver high-efficiency, low-cost AI inference from edge devices to cloud data centers.
- **Entity Type**: Private (Series B – II stage)
- **Headquarters**: Santa Clara, California, United States
- **Founded**: 2022
- **Founders**: Naveen Verma, Ph.D. (CEO) and Kailash Gopalakrishnan, Ph.D. (CTO)

## Core Business
- **Primary industry**: AI semiconductor hardware and embedded software products
- **Target customers**: B2B – enterprises deploying AI at scale, edge-device manufacturers, cloud service providers, and defense/industrial sectors
- **Mission**: Democratize advanced AI by enabling deployment beyond cloud infrastructure to local servers and mobile devices, while slashing costs and environmental impact

## Products & Services
- **Analog In-Memory Computing GPUs & Digital AI Accelerators**: Custom silicon (chiplets, ASICs) and standard-form-factor PCIe cards that perform AI inference using analog computation for orders-of-magnitude better energy efficiency and compute density.
- **Software Stack**: Seamless orchestration layer that supports on-device and cloud deployment, enabling model portability, quantization, and compiler optimizations across EnCharge’s hardware.
- **Edge-to-Cloud Platforms**: Integrated solutions for power-, space-, and cost-constrained environments, covering autonomous systems, smart devices, data center inference, and private on-premise AI.

## Market Standing
- **Valuation / Market Cap**: Not publicly disclosed
- **Key Metrics**: Annual Revenue ~$10M (LinkedIn estimate) | Total Funding $162.9M
- **Notable Investors & Partners**: Tiger Global Management (led $100M Series B, Mar 2025), Anzu Partners (led $21.7M Series A, Dec 2022), DARPA ($18.6M grant, Mar 2024), and others including corporate/institutional backers.
- **Growth Signals**: 
  - 58.6% YoY headcount growth (75 employees, as of mid-2025)
  - 39 active job openings spanning hardware, compiler, and AI architecture roles
  - 150+ patents granted, 300+ technical publications
  - Talent inflows from Intel, IBM, Cerebras, AMD, Meta, Microsoft

## Competitive Advantages
- **Analog In-Memory Computing Moa**t: A proprietary compute architecture that uses charge-domain analog circuits, validated silicon, and leverages existing semiconductor supply chains.
- **Record Efficiency**: Claims 20× higher TOPS/W, 9× higher compute density (TOPS/mm²), 10× lower total cost of ownership, and 100× lower CO₂ emissions compared to leading cloud/GPU alternatives.
- **Deep IP Portfolio**: 150+ granted patents and 300+ publications from 20+ years of foundational research by the founding team (Princeton, IBM, etc.).
- **End-to-End Solution**: Full-stack hardware and software (compiler, quantization, runtime) designed for seamless edge-to-cloud orchestration without vendor lock-in.

## Strategic Focus
- Scale production and customer deployments of their analog in-memory compute chips for high-volume edge and data center inference.
- Expand software ecosystem to support mainstream AI frameworks (PyTorch, TensorFlow, ONNX) and enable easy drop-in replacement for existing GPU-accelerated workloads.
- Deepen partnerships with defense (DARPA) and enterprise cloud providers, emphasizing data privacy, security, and sustainability.
- Double down on sustainability messaging (100× lower CO₂) to meet ESG mandates in enterprise AI procurement.

## Why Work Here
- **Mission-Driven Impact**: Opportunity to make AI accessible to the “99%” by dramatically reducing energy and cost barriers. Work is cited as a “once-in-a-lifetime” chance by leadership.
- **World-Class Team**: Colleagues include industry luminaries from Princeton, IBM, and top semiconductor houses; 57% of staff are in technical roles (engineering, research, compiler).
- **Culture of Collaboration & Innovation**: The careers page highlights integrity, growth, and collaborative problem-solving in a fast-paced startup environment.
- **Comprehensive Rewards**: Benefits package includes typical startup perks; equity likely offered given funding stage.
- **Work Policy**: Hybrid presence indicated by offices in Santa Clara, Canada, Germany, Norway, South Korea, and India. Remote flexibility likely for some roles.
- **Active Hiring**: 39 open positions across DFT, physical design, compiler engineering, and NPU architecture – strong signal of scaling and technical investment.

## Sources
1. [EnCharge AI Official Website](https://www.enchargeai.com/)
2. [EnCharge AI Careers Page](https://www.enchargeai.com/careers)
3. [EnCharge AI About Us (Leadership & Founders)](https://www.enchargeai.com/about-us)
4. [EnCharge AI LinkedIn Company Page](https://www.linkedin.com/company/encharge-ai)
5. [CB Insights Profile – EnCharge AI](https://www.cbinsights.com/company/encharge-ai)

## Other roles at EnCharge AI

- [AI Software Engineer, Agent Harness](https://feeny.ai/job/ai-software-engineer-agent-harness-encharge-ai-india-1x9d8dvk3xvj) — India
- [Staff Physical Design Engineer](https://feeny.ai/job/staff-physical-design-engineer-encharge-ai-us-vva2w6eepdbk) — Us-, Canada
- [Technical Program Manager - Embedded Software](https://feeny.ai/job/technical-program-manager-embedded-software-encharge-ai-united-states-w18v49ve3s0r) — United States
- [Principal Solutions Engineer](https://feeny.ai/job/principal-solutions-engineer-encharge-ai-united-states-vgghgxj68g9h) — United States
- [Lead DFT Engineer](https://feeny.ai/job/lead-dft-engineer-encharge-ai-canada-united-states-q4ggksnf4q7g) — Canada / United States
- [Senior PD Engineer: Synthesis & STA](https://feeny.ai/job/senior-pd-engineer-synthesis-sta-encharge-ai-bengaluru-wfbtaq6984et) — Bengaluru, India
- [Senior Staff / Principal SOC Floorplan Lead](https://feeny.ai/job/senior-staff-principal-soc-floorplan-lead-encharge-ai-bengaluru-5rjzbdmx1e0r) — Bengaluru, India
- [Staff Engineer: STA Methodology & Sign-off Lead](https://feeny.ai/job/staff-engineer-sta-methodology-sign-off-lead-encharge-ai-bengaluru-dnr9280vbw00) — Bengaluru, India
- [Principal SOC Physical Verification & Integration Specialist](https://feeny.ai/job/principal-soc-physical-verification-integration-specialist-encharge-ai-bengaluru-z28meksf9r5v) — Bengaluru, India
- [Staff / Senior Staff CAD & Methodology Engineer (Digital Implementation & Signoff)](https://feeny.ai/job/staff-senior-staff-cad-methodology-engineer-digital-implementation-signoff-bbfjk21sk0rk) — Bengaluru, India