---
title: 'Power Management Architect at Velaura'
canonical: 'https://feeny.ai/job/power-management-architect-velaura-santa-clara-bg8haxw2f67v'
type: 'job'
last_seen: '2026-09-11'
---

# Power Management Architect at Velaura

- **Company:** Velaura
- **Location:** Santa Clara, CA
- **Compensation:** $200k–$300k
- **Employment:** full-time
- **Work type:** onsite
- **Posted:** 2026-07-27
- **Last confirmed live:** 2026-09-11
- **Apply:** https://jobs.lever.co/velaura/fbf10820-522d-4244-aba9-5d5d51a2ea5c

## Job description

## Role Overview

Velaura is designing the compute silicon that powers robots, autonomous systems, and intelligent machines that operate in the physical world—where energy is scarce, thermal headroom is limited, and every milliwatt affects range, runtime, and performance. As Power Management Architect for our Physical AI System-on-Chip (SoC), you will own the power architecture of our silicon: defining how the chip delivers, distributes, and manages energy across compute, AI/NPU, memory, and I/O so that our platforms hit their performance targets within tight power and thermal budgets. This is a foundational, cross-cutting role spanning silicon, firmware, platform software, and product teams. You will set Velaura’s power management strategy from the earliest architecture phase through tape-out and production—shaping power delivery, voltage and frequency scaling, low-power states, and the hardware/software control that keeps Physical AI systems efficient in the field.

## Responsibilities

- Own the SoC power architecture: define power domains, voltage/frequency (DVFS) strategy, power states, and the power delivery network across Velaura’s Physical AI silicon roadmap.

- Define dynamic and static power management techniques including clock and power gating, adaptive voltage scaling, body biasing, and retention strategies, to maximize performance-per-watt for AI and real-time workloads.

- Establish power and energy budgets and model them across use cases; drive power, performance, and area (PPA) trade-offs with architecture, design, and product teams.

- Architect the on-die power management and control subsystem—PMIC interface, power management controller, sensors, and telemetry—and the firmware/software policies that drive it.

- Partner with silicon design, firmware, thermal, package, and platform software teams to embed power intent (e.g., UPF) into the design flow and validate it through implementation and silicon bring-up.

- Define power and thermal management for sustained real-world operation, including thermal throttling, energy-aware scheduling, and safe operating limits.

- Establish power architecture standards, modeling methodology, and review practices; mentor engineers and raise the power-engineering bar across the organization.

Required Qualifications

- 8+ years in power management, mixed-signal, or SoC architecture, with significant experience defining power architecture for shipping silicon or embedded platforms.

- Deep expertise in low-power design techniques: multiple power domains, DVFS, clock/power gating, adaptive voltage scaling, retention, and power state management.

- Strong understanding of power delivery networks, PMICs, voltage regulation, and the interaction between power, thermal, and package constraints.

- Hands-on experience with power intent and low-power methodology (e.g., UPF/CPF) and with power modeling and analysis across the SoC design flow.

- Experience working across silicon design, firmware, and platform software to define and validate power management policies from architecture through silicon bring-up.

- Bachelor’s or advanced degree in Electrical/Computer Engineering or a related field, or equivalent practical experience.

- Excellent written and verbal communication skills, with a track record of influencing technical direction and mentoring engineers.

## Preferred Qualifications

- Experience optimizing power for AI/ML accelerators or NPUs and for real-time or latency-sensitive edge workloads.

- Familiarity with robotics, automotive, mobile, or other power- and thermally-constrained domains, and with battery and energy-storage considerations.

- Experience with energy-aware software/firmware, thermal management, and silicon power characterization and correlation.

- Prior experience at an early-stage or high-growth semiconductor or hardware company, building power architecture and methodology from the ground up.

Why Velaura? Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world. This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

## Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans. Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: careers@velaura.ai. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

## About Velaura

## Company Overview
- **One-liner**: Velaura (formerly Auradine) is a semiconductor and systems company building ultra-low-power compute infrastructure for AI workloads across cloud, edge, and physical AI applications.
- **Entity Type**: Private (Series C, $314M total funding)
- **Headquarters**: Santa Clara, California, USA
- **Founded**: 2023 (as Auradine; rebranded to Velaura AI in 2026)
- **Founders**: Co-founded by Rajiv Khemani (CEO), YJ Kim (President, Products), Sanjay Gupta (President, Strategy & GTM), and Manu Gulati (Chief Development Officer)

## Core Business
- **Primary Industry**: Semiconductor design, AI compute infrastructure, ultra-low-power ASICs
- **Target Customers**: Hyperscale data centers, AI/ML platform providers, edge computing companies, and physical AI (robotics, automotive) OEMs — primarily **B2B Enterprise**
- **Mission**: To deliver proven, breakthrough, ultra-low-power compute for cloud, edge, and physical AI applications, solving the power bottleneck that constrains AI scaling.

## Products & Services
- **Proprietary Ultra-Low-Power Digital Design Technology**: Patented IP and toolflow that reduces power consumption of arithmetic operations by 2–4x on leading process nodes, translating to ~$650–$1,300/chip in power savings over 3 years. Output is optimized GDS or chiplets.
- **Custom AI Accelerators (ASICs)**: Full-custom silicon solutions for AI inference and training workloads, co-designed with customers (RTL input → optimized GDS).
- **Engagement Model**: Customer provides RTL design and priorities; Velaura applies its proprietary methodology, low-voltage libraries, and custom circuit expertise to deliver power-optimized chip designs with proven yield and reliability.

## Market Standing
- **Valuation/Market Cap**: Not publicly disclosed (private company)
- **Key Metric**: **$314M total funding** across 4 rounds
  - Series A (2023): $71M from 6 investors
  - Debt Financing (2023): $10M
  - Series B (2024): $80M from 7 investors
  - Series C (2025): $153M from 8 investors
- **Notable Investors/Partners**: Backed by top-tier VCs (specific names not publicly listed; investors include firms with deep semiconductor expertise) — talent sources include Qualcomm, Arm, Apple, Google, NVIDIA, Intel, Palo Alto Networks, Stripe
- **Growth Signals**:
  - Rebranded from Auradine to Velaura AI in August 2026, signaling strategic expansion into AI compute
  - Added Manu Gulati (ex-NUVIA co-founder, Apple/Google silicon architect) as Co-founder & Chief Development Officer
  - Added Aditya Grover (Co-founder & CTO of Inception, Stanford PhD, part of the team that invented Diffusion models) as Founding Advisor
  - Workforce of 42 employees growing at +4.3% monthly; headcount split ~47% US / 39% India
  - Offices in Santa Clara, CA (HQ) and additional US location, with hiring across hardware and software engineering in Bangalore, Austin, and Boston

## Competitive Advantages
- **Patented ultra-low-power digital design technology** field-proven over multiple years across tens of millions of ASICs deployed with world-class yield and reliability
- **Founding team with exceptional pedigree**: seasoned entrepreneurs and technologists from Qualcomm, Marvell, NVIDIA, Intel, Palo Alto Networks, Apple, Google, and NUVIA (acquired by Qualcomm for ~$1.5B)
- **Systems-level thinking**: combines deep silicon expertise with AI/ML domain knowledge to tackle power as the primary bottleneck for AI at scale
- **Engagement model** that allows customers to leverage Velaura’s IP without fully outsourcing chip design — outputs optimized GDS or chiplets on latest process nodes

## Strategic Focus
- **Scale ultra-low-power compute across three domains**: cloud data centers, edge/enterprise, and physical AI (robotics, autonomous systems)
- **Hire aggressively** for engineering leadership: compiler development, platform software, CAD/methodology, RTL, design verification, advanced packaging, AI architecture, and hardware/software co-design
- **Productize its proprietary IP** into standard offerings for hyperscalers and AI chip companies
- **Continue raising capital** (largest round was $153M Series C in April 2025) to fund expansion

## Why Work Here
- **Culture**: Deep engineering DNA and systems-level thinking — the team is solving one of AI’s hardest physical constraints (power) with proven silicon technology
- **Growth trajectory**: Rapidly scaling startup (42 employees, +4.3% monthly headcount growth, $314M raised) with a clear path to becoming a key infrastructure provider for the AI era
- **Leadership**: Led by industry veterans (NUVIA, Apple, Google, Qualcomm) who have built billion-dollar silicon companies and products powering billions of devices
- **Work environment**: On-site roles in Santa Clara, CA; Austin, Texas; and Bangalore, India. Remote/hybrid policy not specified but multiple office locations suggest flexible collaboration.
- **Impact**: Opportunity to work on cutting-edge AI hardware design, from architecture through tape-out and deployment, with direct impact on the power efficiency of the world’s largest AI clusters
- **Notable perks**: Not publicly detailed, but the company’s focus on high-end engineering talent suggests competitive compensation, equity, and exposure to top-tier semiconductor and AI technology

## Sources
1. [velaura.ai](https://velaura.ai/introducing-velaura-ai/)
2. [velaura.ai](https://velaura.ai/team/)
3. [velaura.ai](https://velaura.ai/low-power-ai-compute/)
4. [jobs.lever.co/velaura](https://jobs.lever.co/velaura/)
5. [linkedin.com](https://linkedin.com/company/velaura-ai-inc)
6. [wellfound.com](https://wellfound.com/company/velaura-ai) (Apollo data extracted on financials and headcount)

SUGGESTED_INDUSTRY: semiconductor-manufacturing-robotics-ai-infrastructure
_(Note: The above slug is not in the provided list. Closest match from the list is `artificial-intelligence`. However, given the company's core business is semiconductor design and power-efficient AI compute infrastructure, `manufacturing-robotics` or `infrastructure` also fit. For strict adherence to the provided list: `artificial-intelligence` is the best single choice.)_

## Other roles at Velaura

- [Office Admin / Receptionist](https://feeny.ai/job/office-admin-receptionist-velaura-santa-clara-asc5tq6ff9ze) — Santa Clara, CA
- [Sr Engineer CAD Pre-Silicon Front End](https://feeny.ai/job/sr-engineer-cad-pre-silicon-front-end-velaura-santa-clara-91g66vhzqqt3) — Santa Clara, CA
- [Director of IT Infrastructure & Operations](https://feeny.ai/job/director-of-it-infrastructure-operations-velaura-santa-clara-46t1yb690v9g) — Santa Clara, CA
- [RTL Power Engineer](https://feeny.ai/job/rtl-power-engineer-velaura-santa-clara-jyj4n03rckrf) — Santa Clara, CA
- [Design Verification Engineer- AI Accelerator](https://feeny.ai/job/design-verification-engineer-ai-accelerator-velaura-santa-clara-15tk23smaz5x) — Santa Clara, CA
- [Design Verification Engineer- CPU](https://feeny.ai/job/design-verification-engineer-cpu-velaura-santa-clara-d1bkx2h2dj9g) — Santa Clara, CA
- [Physical Verification Engineer (Staff / Sr. Staff)](https://feeny.ai/job/physical-verification-engineer-staff-sr-staff-velaura-bengaluru-4k6ypqtyjv23) — Bengaluru, India
- [CAD & Engineering Infrastructure Lead](https://feeny.ai/job/cad-engineering-infrastructure-lead-velaura-santa-clara-eca75sba2s9n) — Santa Clara, CA
- [Senior Technical Recruiter – Engineering](https://feeny.ai/job/senior-technical-recruiter-engineering-velaura-santa-clara-v66mv6d4ghqd) — Santa Clara, CA
- [Principal AI SoC Runtime Software Architect](https://feeny.ai/job/principal-ai-soc-runtime-software-architect-velaura-santa-clara-bf6ceyep3azn) — Santa Clara, CA