---
title: 'Principal AMS Design at Delos Data Inc'
canonical: 'https://feeny.ai/job/principal-ams-design-delos-data-inc-taiwan-j56g64ktnsvy'
type: 'job'
last_seen: '2026-09-15'
---

# Principal AMS Design at Delos Data Inc

- **Company:** Delos Data Inc
- **Location:** Taiwan
- **Employment:** full-time
- **Posted:** 2026-09-14
- **Last confirmed live:** 2026-09-15
- **Apply:** https://jobs.ashbyhq.com/delos-data/7fbefc49-7488-4593-bbbf-d4d6e12e7363

## Job description

Principal AMS Engineer - Taiwan Who we are: We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.

The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.

Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What we need: We are looking for a Principal AMS Engineer to help architect, design, integrate, and validate the high-speed analog and mixed-signal technologies at the core of our products. This is a highly technical, hands-on role spanning AMS/PHY architecture, circuit design, SoC integration, high-speed interfaces, clocking, power, package and board interaction, and silicon validation. You will work across the full development lifecycle—from early architecture and IP definition through implementation, tapeout, bring-up, and mass production. The right person is comfortable operating beyond an individual circuit block. You understand how PHY, analog, digital, package, PCB, power, timing, and system-level considerations interact and can drive solutions across those boundaries. Key Responsibilities:

- Architect and develop analog and mixed-signal circuits and subsystems for next-generation high-speed interfaces and SoCs.
- Lead architecture and integration of high-speed PHY technologies, including die-to-die, UCIe-class interfaces, DDR, HBM, and related SerDes/PHY functions.
- Guide development of critical AMS functions including clocking, reference circuits, DLL/PLL-related functions, voltage monitoring, calibration, data-path circuitry, and other custom analog IP.
- Drive chip/package/PCB co-design for high-speed signal and power integrity.
- Own AMS for PHY integration into complex SoCs, including interface definition, floorplanning, clocking, timing, power intent, IO, and physical implementation considerations.
- Partner closely with digital design, verification, physical design, package, systems, and software teams to resolve cross-domain design issues.
- Develop and improve methodologies for signal integrity, power integrity, timing, low-power design, and system-level analysis.
- Define requirements and evaluate internal and third-party analog, PHY, and interface IP.
- Provide technical leadership for engagement with external IP, design-service, and technology partners.
- Drive designs from pre-silicon architecture and verification through tapeout, bring-up, characterization, post-silicon validation, and production.
- Diagnose complex performance and integration issues across silicon, package, board, and system boundaries.
- Provide technical leadership, design reviews, mentoring, and architectural guidance across the engineering organization.
- Help establish the design flows, standards, and infrastructure needed to build a world-class AMS capability from the ground up.

Required Skills and Qualifications:

- Master’s degree or Ph.D. in Electrical Engineering, Electronics Engineering, Microelectronics, or a related field, or equivalent practical experience.
- Deep experience in analog and mixed-signal IC design and implementation.
- Strong background in high-speed PHY architecture and design, such as DDR, HBM, die-to-die, UCIe, SerDes, MIPI, or similar interfaces.
- Experience developing and integrating analog IP such as PLLs/DLLs, clocking circuits, voltage/reference circuits, ADCs/DACs, LDOs, IO, or related mixed-signal functions.
- Strong understanding of SoC integration, including clocking, timing/STA, low-power design, UPF, IO integration, physical design interaction, and floorplanning.
- Experience with high-speed signal integrity and power integrity across chip, package, and PCB.
- Demonstrated ability to take complex silicon designs from architecture through tapeout and post-silicon validation.
- Experience working closely with package, board, digital, verification, physical-design, and system engineering teams.
- Strong technical judgment and the ability to independently drive ambiguous, cross-functional engineering problems.
- Ability to influence architecture and technical direction without relying on organizational authority.

Desired Skills:

- Direct experience with UCIe or proprietary die-to-die interfaces.
- Experience with advanced packaging, chiplets, or multi-die systems.
- Experience developing complete PHY subsystems from architecture through silicon validation.
- Background in IO/ESD and latch-up design and qualification.
- Experience with analog timing characterization and design-flow/CAD infrastructure.
- Experience managing or technically leading third-party IP and design-service vendors.
- Experience building new design teams, flows, or technical capabilities from the ground up.
- Prior technical leadership or mentoring experience across AMS, PHY, DV, or SoC integration teams.

## Compensation

Competitive compensation aligned with Taiwan senior engineering roles. Exact compensation will vary based on experience and location. We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.

Agency Note: We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.

## About Delos Data Inc

## Company Overview
- **One-liner**: Delos Data builds a new interconnect architecture and server design purpose-built for AI inference, enabling faster, more scalable inference by eliminating network bottlenecks.
- **Entity Type**: Private (Stealth/Seed stage)
- **Headquarters**: Palo Alto, California, USA
- **Founded**: 2025
- **Founders**: Ed Doe (CEO & Co-Founder), Dan Daly (CTO & Co-Founder)

## Core Business
- **Primary Industry**: Semiconductor Manufacturing / AI Infrastructure
- **Target Customers**: Hyperscalers, AI infrastructure builders, and enterprises scaling AI inference workloads (B2B)
- **Mission/Purpose**: To deliver the world's most capable and responsive intelligence by building an interconnect purpose-built for AI inference, not borrowed from HPC, cloud, or training.

## Products & Services
- **Nonstop AI™**: A new cluster architecture and server design that accelerates AI inference through cabled scale-up. It reduces GPU idle time caused by data center interconnect bottlenecks and is designed to flexibly scale to thousands of GPUs, CPUs, and accelerators.
- **Delos Server**: Brings scale-up IO to the network fabric, enabling larger scale-up domains for inference.
- **Delos Mosaic™**: Software providing fine-grained visibility into the scale-up domain, allowing for real-time inference bottleneck detection and AI workload tuning.

## Market Standing
- **Valuation**: Not publicly disclosed (Private, early-stage company)
- **Key Metric**: Total funding not publicly disclosed; company is in early access deployment with select customers.
- **Notable Investors/Partners**: Not publicly disclosed; company exhibited at NVIDIA GTC 2026 (Booth 150) and will demonstrate at Computex 2026 (Booth J1328).
- **Growth Signals**: 
  - Founded in 2025, already has 3 employees with 25% monthly headcount growth.
  - 7 active job postings as of mid-2026.
  - Announced Nonstop AI™ architecture in May 2026 with early access deployments.
  - Exhibited at major industry events (NVIDIA GTC 2026, Computex 2026).
  - Website traffic growing 39.4% month-over-month.

## Competitive Advantages
- **Purpose-built for inference**: Unlike competitors who borrow interconnects from HPC, cloud, or training, Delos Data builds an interconnect specifically designed for AI inference workloads.
- **Cabled scale-up architecture**: Enables flexible scaling to thousands of GPUs, CPUs, and accelerators, reducing GPU idle time caused by network bottlenecks.
- **Full-stack approach**: Combines hardware (Delos Server), software (Delos Mosaic™), and silicon expertise to deliver a unified system-level solution.
- **Ecosystem compatibility**: Built to work within today's GPU and accelerator ecosystems, making adoption easier for hyperscalers and enterprises.
- **Founding team pedigree**: CTO Dan Daly and CEO Ed Doe bring deep expertise from leading semiconductor and AI companies.

## Strategic Focus
- **Product launch and market entry**: Currently in early access with select customers, with broader availability planned for Q4 2026.
- **Scaling the team**: Actively hiring across engineering (system software, DFT, verification, SDET), advanced packaging, and people operations roles.
- **Building the brand**: Establishing presence at major industry events (NVIDIA GTC, Computex) to build credibility and attract top talent.
- **Targeting hyperscalers and AI infrastructure builders**: The primary customer base for the Nonstop AI™ architecture.

## Why Work Here
- **Mission-driven work**: Opportunity to build foundational infrastructure for the next generation of AI, working on a problem the founders describe as "the next leap in AI performance."
- **Early-stage impact**: Join a company founded in 2025 with only 3 employees, offering significant ownership and influence over product and culture.
- **Hybrid/Remote flexibility**: Roles are listed as both remote and hybrid (Palo Alto, CA and Montréal, QC, CAN), with a "Remote Workspace" designation for many positions.
- **Founding team**: Work directly under experienced leadership (CTO Dan Daly, CEO Ed Doe) with deep expertise in semiconductors and AI.
- **Cutting-edge tech stack**: Work with Kubernetes, PyTorch, CUDA, SystemVerilog, Python, Terraform, and more across hardware and software domains.
- **High-growth trajectory**: 25% monthly headcount growth, active hiring across 7+ roles, and strong momentum from major industry events.

## Sources
1. [delosdata.com](https://delosdata.com/)
2. [builtin.com](https://builtin.com/company/delos-data)
3. [linkedin.com](https://www.linkedin.com/company/delosdata)
4. [delosdata.com/press](https://www.delosdata.com/press/faster-ai-inference-enabled-by-1000x-higher-scale-with-delos-data-nonstop-ai)
5. [opencorpdata.com](https://opencorpdata.com/us-va/11860584)

## Other roles at Delos Data Inc

- [SerDes Validation Leader](https://feeny.ai/job/serdes-validation-leader-delos-data-inc-remote-cgr5a14pkbw8)
- [Physical Design Engineer](https://feeny.ai/job/physical-design-engineer-delos-data-inc-remote-y6hzv0vsjjdr)
- [Software Development Engineer in Test - AI](https://feeny.ai/job/software-development-engineer-in-test-ai-delos-data-inc-charlottesville-qftkz7gwjb6p) — Charlottesville, VA
- [Software Development Engineer in Test - AI](https://feeny.ai/job/software-development-engineer-in-test-ai-delos-data-inc-palo-alto-h0zdwvb7hn1r) — Palo Alto, CA
- [System Software Engineer - AI](https://feeny.ai/job/system-software-engineer-ai-delos-data-inc-palo-alto-xcxcygvyxje5) — Palo Alto, CA
- [Principal Power Design Engineer](https://feeny.ai/job/principal-power-design-engineer-delos-data-inc-palo-alto-k4t1g4pn932e) — Palo Alto, CA
- [Package Engineer](https://feeny.ai/job/package-engineer-delos-data-inc-palo-alto-0jq1ejpayss3) — Palo Alto, CA
- [Senior Electrical Engineer, Server Hardware 資深伺服器硬體工程師](https://feeny.ai/job/senior-electrical-engineer-server-hardware-delos-data-inc-taiwan-vvrpb87n5qrv) — Taiwan
- [DFT Engineer](https://feeny.ai/job/dft-engineer-delos-data-inc-remote-gb8zfx61v80h)
- [Join the Delos Team!](https://feeny.ai/job/join-the-delos-team-delos-data-inc-remote-1ka64cpztr4b)