---
title: 'Principal Analog Design Engineer at Celero Communications, Inc.'
canonical: 'https://feeny.ai/job/principal-analog-design-engineer-celero-communications-inc-vancouver-british-sz02fec2vbsc'
type: 'job'
last_seen: '2026-09-11'
---

# Principal Analog Design Engineer at Celero Communications, Inc.

- **Company:** Celero Communications, Inc.
- **Location:** Vancouver British Columbia, Canada
- **Posted:** 2026-08-17
- **Last confirmed live:** 2026-09-11
- **Apply:** https://job-boards.greenhouse.io/celerocommunicationsinc/jobs/4372170009

## Job description

Are you an Analog Design Engineer passionate about building the high-speed interconnect technology powering the next generation of AI? Join our fast-growing semiconductor startup and help develop disruptive mixed-signal solutions that enable tomorrow's AI infrastructure. We are seeking experienced Analog Design Engineers to architect, design, and deliver high-performance analog and mixed-signal circuits for next-generation transceivers and other critical high-speed functions. This is an opportunity to work alongside a world-class engineering team, tackle challenging design problems in advanced process technologies, and make a direct impact on innovative products from architecture through silicon.

Locations: Irvine, CA (HQ) | San Jose, CA | Vancouver, BC | Ottawa, ON

What You Will Do:

- High speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.)
- Clock generation and distribution (VCOs, PLL, clock distribution, etc.)
- Fundamental analog blocks (bandgap references, LDOs, temp sensors, etc.)
- New techniques for the development of next generation optical transceiver
- Design of custom passive components, from concept to silicon implementation
- Supervise analog layouts within advanced process nodes
- System verification and circuit design spec creation
- Silicon bring-up, debug and support
- Team communication and documentation

What You Will Bring:

- Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of experience
- Should have strong analog design fundamentals and experience in designing analog circuit blocks for broadband amplification, clock generation and distribution, and/or fundamental analog blocks
- Experience with analog design and verification tools (Virtuoso, Spectre, ADE, and post layout extraction tools) is a must
- Experience in advance CMOS design and verification flows (tools to evaluate self-heating, electromigration, safe operating area)
- Experience with electromagnetic simulation tools (EMX, Momentum, HFSS or other) is a plus
- Knowledge of the fundamentals on electromagnetism, lump models, and high frequency design
- Good understanding of analog layouts in FinFET and its effect on high-speed designs is a plus
- Strong communication and documentation skills

## About Celero Communications, Inc.

## Company Overview
- **One-liner**: Celero Communications develops advanced coherent DSP solutions that enable high-bandwidth, low-power optical connectivity for AI infrastructure, eliminating distance bottlenecks in data centers.
- **Entity Type**: Private (Series B; total funding $148.4M per LinkedIn, $140M per company press release)
- **Headquarters**: Irvine, California, USA
- **Founded**: 2024
- **Founders**: Nariman Yousefi (CEO, President & Co-founder) and Oscar Agazzi (CTO & Co-founder)

## Core Business
- **Primary industry**: Semiconductor manufacturing / optical networking for AI infrastructure
- **Target customers**: B2B – hyperscale data centers, AI cloud providers, and large-scale accelerated computing clusters
- **Mission**: “Deliver the optical performance and scalability needed for the next generation of accelerated computing” [celero.inc](https://celero.inc/about/)

## Products & Services
- **Coherent DSP Platform**: A digital signal processor that provides light-speed performance, bandwidth efficiency, and scalable optical links for AI accelerators, servers, and clusters. The technology is described as 100x more efficient than conventional optical transmission and is designed for interoperability across diverse AI and cloud platforms. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/)

## Market Standing
- **Valuation**: Not publicly disclosed
- **Key Metric**: Total funding of **$148.4 million** (Seed $8.4M led by Sutter Hill Ventures; Venture Round $40M; Series B $100M led by CapitalG) [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Notable Investors/Partners**: Sutter Hill Ventures (lead seed & Series A), CapitalG (lead Series B), plus other undisclosed investors in venture round [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Growth Signals**: Founded in 2024, already employs **93 people** with a monthly headcount growth of **+9.3%**. Operates design centers in Irvine (CA), Ottawa (Canada), and Córdoba (Argentina). [linkedin.com](https://www.linkedin.com/company/celero-communications)

## Competitive Advantages
- **Founding team** consists of industry pioneers from Marvell, Inphi, Broadcom, and ClariPhy with decades of experience in analog design, digital signal processing, and optical networking. [celero.inc](https://celero.inc/about/)
- **Coherent DSP technology** that eliminates distance bottlenecks, delivering 100x more efficient optical transmission for scale-across AI infrastructure. [celero.inc](https://celero.inc/)
- **System flexibility and interoperability** across diverse AI and cloud platforms, making it easier for data centers to adopt. [celero.inc](https://celero.inc/)

## Strategic Focus
- **Current priorities**: Scaling AI infrastructure connectivity by delivering high-bandwidth, low-power optical links; expanding engineering teams across all design centers; and building energy-efficient systems that redefine how data centers connect. [celero.inc](https://celero.inc/careers/)

## Why Work Here
- **Culture**: Described as driven by curiosity, precision, and the challenge of making AI systems faster and more energy-efficient. Employees collaborate with global experts in coherent DSP and optical engineering. [celero.inc](https://celero.inc/careers/)
- **Work model**: On-site/hybrid at three locations – Irvine, CA (HQ); Ottawa, Canada; and Córdoba, Argentina. Multiple engineering roles (Analog Design, ASIC, DSP, Firmware, Verification) are posted with specific location requirements. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc)
- **Notable perks**: Opportunity to work on next-generation AI infrastructure technology alongside industry pioneers. The company emphasizes building scalable, energy-efficient systems and offers roles across R&D, operations, and manufacturing. [celero.inc](https://celero.inc/careers/)

## Sources
1. [celero.inc](https://celero.inc/) – Company homepage and product description
2. [celero.inc](https://celero.inc/about/) – About page (founding, leadership, mission)
3. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/) – Press release on $140M funding
4. [linkedin.com](https://www.linkedin.com/company/celero-communications) – LinkedIn company page (funding details, headcount, locations, employee breakdown)
5. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc) – Careers page (open positions, locations)

## Other roles at Celero Communications, Inc.

- [High-Speed Analog Layout Design Engineer](https://feeny.ai/job/high-speed-analog-layout-design-engineer-celero-communications-inc-cordoba-66dn2b6kaepy) — Córdoba, Argentina
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-jjzw8wst9kw4) — Ottawa, Canada
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-xb3kfd5e3s5y) — San Jose, CA
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-vahmmaqvrh01) — Irvine, CA
- [IT Help Desk](https://feeny.ai/job/it-help-desk-celero-communications-inc-cordoba-a16t8nfqdwcf) — Córdoba, Argentina
- [ASIC Design Engineer – DSP / Analog / SerDes](https://feeny.ai/job/asic-design-engineer-dsp-analog-serdes-celero-communications-inc-ottawa-pd4fx2w60yhv) — Ottawa, Canada
- [ASIC Design Engineer – DSP / Analog / SerDes](https://feeny.ai/job/asic-design-engineer-dsp-analog-serdes-celero-communications-inc-irvine-we9e7z3fvx1m) — Irvine, CA
- [Principal Product Engineer](https://feeny.ai/job/principal-product-engineer-celero-communications-inc-singapore-derwypn4kenf) — Singapore
- [Principal Analog Design Engineer](https://feeny.ai/job/principal-analog-design-engineer-celero-communications-inc-ottawa-eqcyjq44gc71) — Ottawa, Canada
- [Principal Analog Design Engineer](https://feeny.ai/job/principal-analog-design-engineer-celero-communications-inc-irvine-52w2zch5xq3q) — Irvine, CA