--- title: 'Principal Analog Design Engineer at Neurophos' canonical: 'https://feeny.ai/job/principal-analog-design-engineer-neurophos-sunnyvale-kz1chpqbswbd' type: 'job' last_seen: '2026-09-14' --- # Principal Analog Design Engineer at Neurophos - **Company:** Neurophos - **Location:** Sunnyvale, CA - **Compensation:** $225k–$280k - **Employment:** full-time - **Work type:** onsite - **Posted:** 2025-12-17 - **Last confirmed live:** 2026-09-14 - **Apply:** https://jobs.ashbyhq.com/neurophos/aa626cda-b00c-4a45-ac32-305a468d1b86 ## Job description ## About Neurophos The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach. Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference. We’ve assembled a world-class team of industry veterans and recently raised a [$110M Series A](https://www.neurophos.com/110m-raise) led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. Join us and shape the future of computing! Position Overview: We are seeking a seasoned Principal Analog Design Engineer to play a vital role in developing cutting-edge full-custom electronic transceiver components that interface directly with our custom silicon photonics and are essential to our revolutionary photonic AI platform. You will be responsible for the full lifecycle of analog blocks, from specification and architecture down to tape-out-ready layout. Success in this role requires a deep understanding of transistor-level circuit design, linearity, noise performance, and signal integrity in CMOS processes up to GHz speeds. If you possess a proven track record of designing robust, ultra-fast analog circuits and are eager to work at the intersection of electronics and photonics, you will make a defining impact on the future of optical computing. Location: San Jose, CA or Hsinchu, Taiwan. Full-time onsite position. Key Responsibilities: - Design, simulate, and verify high-speed analog circuits, including but not limited to high-swing drivers, transimpedance amplifiers, ADCs, DACs, and PLLs, in deep-submicron CMOS technologies. - Define architecture and specifications for electronic blocks based on system-level requirements. - Perform full-custom schematic capture, advanced analog simulations, and complete physical layout, including DRC/LVS, of critical analog blocks using Cadence Virtuoso. - Ensure rigorous signal integrity and power integrity across all high-speed interconnects. - Conduct layout floor planning. - Conduct post-layout extraction and simulation to validate performance against parasitic effects. - Collaborate closely with the Photonics and Digital teams to optimize the electro-optic interface, maximizing performance across the combination of disciplines. - Collaborate with team members to prepare and conduct the bench characterization and production tests. Qualifications: - MS or PhD in Electrical Engineering. - 10+ years of professional experience in full-custom analog integrated circuit design, 5+ years of dedicated experience in either GHz-speed RF or GHz-speed broadband analog design. - Demonstrated expert proficiency in the Cadence tool suite, specifically Virtuoso schematic, simulation, and custom layout. - Deep understanding of semiconductor device physics, linearity, noise analysis, and high-frequency circuit theory. - Proven track record of taking high-speed analog blocks from concept to mass production (successful tape-outs). Preferred Skills: - A background in photonic transceivers or optical communication electronics. - Extensive design experience in TSMC latest technology nodes, such as N5P, N3P, and N2P. - Experience designing high-speed data converters. - Experience designing low-jitter clocking circuits, including PLLs. - Proficiency in electromagnetic simulation tools such as EMX or HFSS. - Experience with frequency domain simulation in Spectre RF. ## What We Offer This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world. ## Benefits Join a team that invests in your future and your well-being. At Neurophos, we offer: - 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions. - Unlimited PTO. No rigid vacation banks, just a focus on delivery. - 401(k) matching and stock option opportunities to ensure our success is your success. - Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance. - Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t. ## About Neurophos ## Company Overview - **One-liner**: Neurophos develops photonic AI chips (Optical Processing Units) that perform matrix multiplications at the speed of light, aiming to replace traditional GPUs in data-center inference workloads. - **Entity Type**: Private, Series A - **Headquarters**: Austin, Texas, USA (with an additional office in San Jose, California) - **Founded**: 2020 - **Founders**: Patrick Bowen (CEO, Co-Founder) and Andrew Traverso (Chief Scientist, Co-Founder); other co-founders may include Preston Woo and Hod Finkelstein (CEO, CTO roles indicated on team page). ## Core Business - **Primary industry**: Semiconductor / Photonic AI Hardware - **Target customers**: B2B – hyperscale data centers, enterprise AI infrastructure providers - **Mission/purpose**: “We’re building the first programmable light-speed computer” – solving energy and scalability challenges in AI data centers by using optical rather than electronic computation. ## Products & Services - **Optical Processing Unit (OPU)**: A photonic AI chip that integrates over one million micron-scale optical processing components on a single die. It performs matrix multiplications in-memory at the speed of light, delivering up to 100x the energy efficiency of traditional GPUs and NVIDIA servers while fitting in a single-GPU form factor. The chip uses an active, programmable metasurface and silicon photonics to achieve 0.47 ExaOPS performance in a 1m x 1m footprint. First systems are targeted for early 2028, with production ramp in mid-2028. ## Market Standing - **Valuation/Market Cap**: Not disclosed - **Key Metric**: Total funding raised = **$119.2M** (including a $110M Series A closed in early 2026) - **Notable Investors**: Gates Frontier (lead), M12 (Microsoft’s venture fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, MetaVC Partners, Gaingels, Mana Ventures, and 22+ others. - **Growth Signals**: - Recognized on EE Times Silicon 100 list for several consecutive years. - Over 300 patents filed and protected. - Rapid hiring after Series A – “hypergrowth phase” as per press release. - Team includes veterans from NVIDIA, AMD, Apple, Meta, Google, Magic Leap, Micron, Qualcomm, Samsung, and other photonic/AR companies. ## Competitive Advantages - **Metasurface optical transistors** that are **10,000x smaller** than traditional photonic components, enabling unprecedented density – millions of weights fit in the area of a postage stamp. - **300+ patents** covering optical metamaterials, neural network accelerators, and machine learning hardware. - **Energy efficiency**: Up to 100x improvement over existing electronic solutions (e.g., GPUs), directly addressing the power constraints of hyperscale AI inference. - **Size/performance**: OPU delivers the performance of a 3,000-pound server in the size and power envelope of a single GPU. ## Strategic Focus - **Commercialization**: First customer evaluations begin in 2026; first OPU systems target early 2028 production ramp. - **Talent acquisition**: Scaling the team aggressively across analog design, photonics, architecture, and software to meet “hypergrowth” demand. - **Partnerships**: Leveraging investors like Bosch Ventures (industrial IoT), Aramco Ventures (energy), and M12 (cloud/AI) to align with large-scale data center customers. ## Why Work Here - **Culture**: In-office, on‑site work culture in Austin, TX (primary) and San Jose, CA. Described as a “world-class team” with leaders from top semiconductor and tech companies. - **Growth**: Joining at a hypergrowth scale‑up stage with significant funding and a clear path to production; opportunities to shape the architecture and engineering of a new computing paradigm. - **Engineering focus**: 34 out of 40 total employees are in product + tech roles, indicating a highly technical, R&D-driven environment. - **Impact**: Work on cutting-edge optical computing that could redefine AI hardware efficiency; involvement in everything from silicon photonics to compiler software. - **Notable perks**: Not explicitly listed, but being a well-funded deep-tech startup likely offers competitive equity, technical challenges, and direct mentorship from industry veterans. ## Sources 1. [neurophos.com](https://www.neurophos.com/) 2. [neurophos.com/careers](https://www.neurophos.com/careers) 3. [neurophos.com/team](https://www.neurophos.com/team) 4. [cbinsights.com](https://www.cbinsights.com/company/neurophos) 5. [builtin.com](https://builtin.com/company/neurophos) ## Other roles at Neurophos - [Staff Technical Program Manager, ASIC](https://feeny.ai/job/staff-technical-program-manager-asic-neurophos-austin-mhx7d9bs15a4) — Austin, TX - [Staff Modeling Architect](https://feeny.ai/job/staff-modeling-architect-neurophos-austin-8cedvv6953bg) — Austin, TX - [Senior Modeling Architect, Performance Benchmarking](https://feeny.ai/job/senior-modeling-architect-performance-benchmarking-neurophos-austin-rpy828cj7yrc) — Austin, TX - [Modeling Architect](https://feeny.ai/job/modeling-architect-neurophos-austin-ew2q0rxv7e3b) — Austin, TX - [Principal SoC Design Engineer / SoC Lead](https://feeny.ai/job/principal-soc-design-engineer-soc-lead-neurophos-austin-ghf226b0sp4d) — Austin, TX - [Physical Design / Implementation Lead](https://feeny.ai/job/physical-design-implementation-lead-neurophos-austin-jge0dfb6md1v) — Austin, TX - [Senior/Staff Applied Scientist, Numerical Optimization & Quantization](https://feeny.ai/job/senior-staff-applied-scientist-numerical-optimization-quantization-neurophos-jgmrpeawfsp5) — Austin, TX - [Principal Fabric/Network Architect](https://feeny.ai/job/principal-fabric-network-architect-neurophos-sunnyvale-zq97mx2rm8r3) — Sunnyvale, CA - [Principal Platform Security Architect](https://feeny.ai/job/principal-platform-security-architect-neurophos-sunnyvale-fw052b83t93h) — Sunnyvale, CA - [Lead IT Engineer](https://feeny.ai/job/lead-it-engineer-neurophos-austin-jegb2gkjwpgy) — Austin, TX