--- title: 'Principal PCS/PMA RTL Design Engineer at Astera Labs' canonical: 'https://feeny.ai/job/principal-pcs-pma-rtl-design-engineer-astera-labs-san-jose-v0c0r56v3krf' type: 'job' last_seen: '2026-11-06' --- # Principal PCS/PMA RTL Design Engineer at Astera Labs - **Company:** Astera Labs - **Location:** San Jose, CA - **Posted:** 2026-11-03 - **Last confirmed live:** 2026-11-06 - **Apply:** https://job-boards.greenhouse.io/asteralabs/jobs/4733832005 ## Job description Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at [www.asteralabs.com](http://www.asteralabs.com/). Principal PCS/PMA RTL Design Engineer Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards such as Ethernet, PCIe, UCIe, and UALink. You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs. You will work with experienced architects and design engineers to translate microarchitectural specifications into robust, synthesizable RTL. You will collaborate closely with SerDes/analog, verification, physical design, DFT, firmware, systems, and validation teams to deliver reliable designs through synthesis, timing closure, tapeout, and silicon validation. This is a hands-on opportunity for an engineer who wants to build expertise in multi-protocol, multi-lane PHY digital design and contribute to products that enable next-generation AI and cloud infrastructure. ## Key responsibilities PCS/PMA RTL design and implementation - Develop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols. - Implement PCS functions such as line encoding/decoding (64b/66b, 128b/130b, 8b/10b), scrambling/descrambling, block and word alignment, lane deskew and reordering, gearboxes, elastic buffers/FIFOs, and rate adaptation. - Implement forward error correction (e.g., RS-FEC/KP4, FEC framing, interleaving), plus the related error counters and status logic. - Implement PMA digital interface logic, including SerDes datapath interfaces (PIPE, SerDes-facing parallel interfaces, UCIe PHY/raw-die interfaces), clock and data recovery (CDR) control interfaces, equalization and link-training control (e.g., PCIe LTSSM equalization, Ethernet auto-negotiation/link training), and calibration and adaptation control. - Design lane-level and multi-lane logic, including lane bonding, polarity and lane reversal, PRBS generation/checking, loopback modes, and BIST features. - Translate architectural and microarchitectural specifications into datapaths, control logic, state machines, register interfaces, and protocol logic. - Design reusable, configurable RTL modules that support multiple protocols, data rates, and lane configurations. - Integrate internal and third-party IP (including analog/mixed-signal PHY macros) while following established design and coding methodologies. - Participate in design reviews and contribute to improvements in RTL quality, reuse, latency, performance, power, and area. Verification and design quality - Collaborate with design verification engineers to define functional requirements, test plans, and coverage goals, including protocol compliance (IEEE 802.3, PCI-SIG, UCIe, UALink specifications). - Debug simulation failures using waveform analysis, assertions, regression results, and root-cause analysis. - Support lint, clock-domain crossing (CDC), reset-domain crossing (RDC), and RTL quality checks, with particular attention to multi-clock-domain PCS/PMA boundaries and asynchronous lane clocks. - Participate in UVM-based verification activities and help resolve functional and integration issues. - Support gate-level simulation and regression debug as required. Synthesis, timing, and implementation - Support logic synthesis, constraints development, and design implementation flows for high-speed, wide-datapath designs. - Perform Static Timing Analysis (STA) and help identify and resolve setup, hold, clock, and interface timing issues, including at the SerDes and PHY boundaries. - Support timing closure, power optimization, and PPA trade-offs in collaboration with synthesis, timing, and physical-design teams. - Assist with DFT integration, scan requirements, low-power intent (including per-lane power states), ECOs, and implementation signoff. - Review reports and debug issues from Cadence and/or Synopsys digital design flows. Silicon and cross-functional collaboration - Support block-level and subsystem-level integration through tapeout milestones. - Collaborate with SerDes/analog, physical design, DFT, firmware, systems, packaging, and validation teams. - Participate in silicon bring-up, link bring-up, interoperability and compliance testing, post-silicon debug, and failure analysis as opportunities arise. - Document design decisions, issues, and technical solutions clearly for cross-functional stakeholders. ## Basic qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. - Master's degree is preferred. - 3+ years of relevant experience in digital ASIC, SoC, or RTL design, or equivalent academic and industry experience. - Hands-on experience with Verilog or SystemVerilog RTL development. - Understanding of digital design fundamentals, including combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces. - Working knowledge of at least one high-speed serial protocol (Ethernet, PCIe, UCIe, UALink, CXL, or similar) at the PCS/PHY layer. - Experience with RTL simulation, debugging, synthesis, and basic timing analysis. - Familiarity with ASIC design flows and collaboration across design and verification teams. - Strong communication skills and the ability to work effectively in a collaborative, fast-paced environment. - Ability and willingness to work onsite in San Jose, California. ## Preferred qualifications - Direct experience designing PCS, PMA, or PHY digital logic for Ethernet (25G–224G per lane, 100G/200G/400G/800G/1.6T), PCIe (Gen4/5/6/7), UCIe, UALink, CXL, or similar standards. - Experience with PAM4 signaling, FEC (RS-FEC/KP4, FLIT-mode FEC/CRC), lane deskew/alignment, link training, and equalization control. - Familiarity with the PIPE specification, 802.3 Clause 73/72/136/162-series, PCIe LTSSM, and UCIe link training and sideband. - Experience with multi-lane, multi-rate SerDes digital datapaths and clocking architectures. - Familiarity with interconnect, networking, or data-center ASICs (retimers, switches, NICs, DPUs, SmartNICs, NoCs). - Familiarity with synthesis and implementation tools such as Cadence Genus/Innovus or Synopsys Design Compiler/ICC2. - Experience with STA using tools such as Synopsys PrimeTime or Cadence Tempus. - Familiarity with lint, CDC/RDC, DFT, scan, GLS, LEC, UPF, or formal-verification flows. - Experience with UVM, SystemVerilog Assertions, functional coverage, or verification-plan development. - Experience with Python, Tcl, Perl, Shell, or other scripting languages for design and verification automation. - Exposure to advanced-node CMOS design (e.g., 5nm/3nm), tapeout, silicon bring-up, or post-silicon validation, including BER measurements and lab debug. - Experience working with physical-design teams on floorplanning, congestion, timing, power, and implementation challenges. Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. ## About Astera Labs ## Company Overview - **One-liner**: Astera Labs designs and delivers semiconductor-based connectivity solutions purpose-built to unleash the full potential of cloud and AI infrastructure. - **Entity Type**: Public (Nasdaq: ALAB) - **Headquarters**: Santa Clara, California, United States - **Founded**: 2017 - **Founders**: Jitendra Mohan, Sanjay Gajendra, Casey Morrison ## Core Business - **Primary industry**: Semiconductor manufacturing / AI infrastructure connectivity - **Target customers**: B2B, primarily hyperscale cloud providers and system OEMs (e.g., NVIDIA, AMD, Intel) - **Mission statement**: To innovate, design, and deliver semiconductor-based connectivity solutions that are purpose-built to unleash the full potential of cloud and AI infrastructure. ## Products & Services - **Aries PCIe®/CXL™ Smart DSP Retimers**: Silicon ICs, boards, and modules that digitally recover degraded high-speed signals to extend reach and enable higher PCIe/CXL data bandwidth between compute, storage, and network controllers. - **Taurus Ethernet Smart Cable Modules™**: Hardware modules that increase network connectivity bandwidth between servers and switches over copper media, removing rack-level Ethernet bottlenecks. - **Leo CXL Memory Connectivity Controllers**: ICs and boards that expand, share, and pool DRAM memory to overcome processor memory bandwidth bottlenecks for AI workloads. - **Scorpio Smart Fabric Switches**: A family of PCIe 6 fabric switches ranging from 32 to 320 lanes, including the new 320-lane Scorpio X-Series Fabric Switch for AI scale-up fabrics. - **COSMOS Software Suite**: A connectivity system management and optimization software that enables configuration, monitoring, troubleshooting, and predictive analytics for all Astera Labs products. ## Market Standing - **Market Cap**: ~$11.6 billion (as of mid-2026) - **Key Metric - Revenue**: $35 million (annual, reported) - **Key Metric - Operating Income**: $173.4 million (2025) - **Key Metric - Net Income**: $219.1 million (2025) - **Total Funding**: ~$810.75 million (pre-IPO), with Series C ($50M, led by Fidelity) and Series D ($150M, led by Fidelity) - **IPO Date**: March 20, 2024 - **Notable Investors/Partners**: Fidelity, NVIDIA, Advanced Micro Devices, Intel, major hyperscalers - **Growth Signals**: 92% YoY headcount growth (675 employees); 144 active job postings (+260% YoY); expanded Taiwan operations with a new Cloud-Scale Interop Lab in 2026; shipping millions of devices across all major hyperscalers; 300+ design wins. ## Competitive Advantages - **First-to-market innovation**: Pioneered first-to-market PCIe, Ethernet, and CXL connectivity products. - **Patented software-defined platform approach**: Differentiates via a platform that combines silicon hardware with embedded COSMOS software, enabling flexibility, observability, and predictive analytics. - **Deep hyperscaler relationships**: Trusted partner to the world’s largest cloud providers, with proven interoperability validated in their own Cloud-Scale Interop Lab. - **Broad product portfolio**: Covers PCIe retimers, Ethernet cable modules, CXL memory controllers, and fabric switches—addressing the full spectrum of AI connectivity bottlenecks. - **Strong IP and engineering talent**: 443 employees in technical roles; talent sourced from Intel (65), Marvell (37), Texas Instruments (40), AMD (22), and NVIDIA. ## Strategic Focus - **Scaling AI infrastructure**: Expanding product portfolio and global footprint (12 countries) to meet surging demand for rack-scale AI. - **Open standards leadership**: All products are grounded in open standards (PCIe, CXL, Ethernet), ensuring interoperability and broad adoption. - **Taiwan expansion**: Growing engineering presence and Interop Lab in Taiwan to strengthen integration with leading AI platform providers and system manufacturers. - **Continued innovation**: Shipping the new 320-lane Scorpio X-Series Fabric Switch and expanding the COSMOS software suite for fleet-level management and optimization. ## Why Work Here - **Culture**: Described as collaborative, ownership-driven, and focused on solving complex problems together. The company emphasizes diversity and inclusion as drivers of creativity and innovation. - **Growth**: Astera Labs supports non-linear career growth—employees can deepen expertise (“scale up”) or broaden into new areas (“scale out”). 92% YoY headcount growth signals rapid expansion and opportunity. - **Remote/Hybrid**: Not explicitly stated, but global operations across 12 countries (including India, Canada, Israel, Taiwan, Vietnam) suggest a flexible, distributed work model. - **Benefits**: Competitive medical, dental, and vision plans; flexible time off; family planning and parental leave; 401K and retirement plans. - **Engineering culture**: Strong focus on cutting-edge semiconductor and AI infrastructure technology. High concentration of senior (24%) and specialist (19%) talent. Active internship and new graduate programs. - **Employee ratings**: 4.5/5.0 on LinkedIn (124 reviews), with high marks for compensation (4.6), culture (4.4), and career development (4.4). ## Sources 1. [Astera Labs Careers Page](https://www.asteralabs.com/careers/) 2. [Astera Labs Official Website](https://www.asteralabs.com/) 3. [Astera Labs LinkedIn](https://www.linkedin.com/company/astera-labs) 4. [Astera Labs Products Page](https://www.asteralabs.com/products/) 5. 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