---
title: 'Principal Physical Design Engineer at Celero Communications, Inc.'
canonical: 'https://feeny.ai/job/principal-physical-design-engineer-celero-communications-inc-san-jose-bef5schrf350'
type: 'job'
last_seen: '2026-09-11'
---

# Principal Physical Design Engineer at Celero Communications, Inc.

- **Company:** Celero Communications, Inc.
- **Location:** San Jose, CA
- **Posted:** 2026-08-17
- **Last confirmed live:** 2026-09-11
- **Apply:** https://job-boards.greenhouse.io/celerocommunicationsinc/jobs/4372151009

## Job description

Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure.

We are seeking an experienced Physical Design Engineer to lead the transformation of complex circuit designs into high-quality, manufacturable silicon. In this role, you will drive all aspects of the physical implementation flow, including floorplanning, power planning, place-and-route (P&R), clock tree synthesis, timing closure, and physical verification. You will collaborate closely with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet aggressive targets for performance, power, area (PPA), signal integrity, and manufacturability. As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor products.

Locations: San Jose, CA (preferred) or Irvine, CA (HQ)

Core Responsibilities

- RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
- Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
- Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
- Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
- Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
- Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness.

## Key Qualifications

- Must have 5+ years of relevant ASIC physical design experience (depending on degree level).
- Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
- Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre).
- Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

## About Celero Communications, Inc.

## Company Overview
- **One-liner**: Celero Communications develops advanced coherent DSP solutions that enable high-bandwidth, low-power optical connectivity for AI infrastructure, eliminating distance bottlenecks in data centers.
- **Entity Type**: Private (Series B; total funding $148.4M per LinkedIn, $140M per company press release)
- **Headquarters**: Irvine, California, USA
- **Founded**: 2024
- **Founders**: Nariman Yousefi (CEO, President & Co-founder) and Oscar Agazzi (CTO & Co-founder)

## Core Business
- **Primary industry**: Semiconductor manufacturing / optical networking for AI infrastructure
- **Target customers**: B2B – hyperscale data centers, AI cloud providers, and large-scale accelerated computing clusters
- **Mission**: “Deliver the optical performance and scalability needed for the next generation of accelerated computing” [celero.inc](https://celero.inc/about/)

## Products & Services
- **Coherent DSP Platform**: A digital signal processor that provides light-speed performance, bandwidth efficiency, and scalable optical links for AI accelerators, servers, and clusters. The technology is described as 100x more efficient than conventional optical transmission and is designed for interoperability across diverse AI and cloud platforms. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/)

## Market Standing
- **Valuation**: Not publicly disclosed
- **Key Metric**: Total funding of **$148.4 million** (Seed $8.4M led by Sutter Hill Ventures; Venture Round $40M; Series B $100M led by CapitalG) [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Notable Investors/Partners**: Sutter Hill Ventures (lead seed & Series A), CapitalG (lead Series B), plus other undisclosed investors in venture round [linkedin.com](https://www.linkedin.com/company/celero-communications)
- **Growth Signals**: Founded in 2024, already employs **93 people** with a monthly headcount growth of **+9.3%**. Operates design centers in Irvine (CA), Ottawa (Canada), and Córdoba (Argentina). [linkedin.com](https://www.linkedin.com/company/celero-communications)

## Competitive Advantages
- **Founding team** consists of industry pioneers from Marvell, Inphi, Broadcom, and ClariPhy with decades of experience in analog design, digital signal processing, and optical networking. [celero.inc](https://celero.inc/about/)
- **Coherent DSP technology** that eliminates distance bottlenecks, delivering 100x more efficient optical transmission for scale-across AI infrastructure. [celero.inc](https://celero.inc/)
- **System flexibility and interoperability** across diverse AI and cloud platforms, making it easier for data centers to adopt. [celero.inc](https://celero.inc/)

## Strategic Focus
- **Current priorities**: Scaling AI infrastructure connectivity by delivering high-bandwidth, low-power optical links; expanding engineering teams across all design centers; and building energy-efficient systems that redefine how data centers connect. [celero.inc](https://celero.inc/careers/)

## Why Work Here
- **Culture**: Described as driven by curiosity, precision, and the challenge of making AI systems faster and more energy-efficient. Employees collaborate with global experts in coherent DSP and optical engineering. [celero.inc](https://celero.inc/careers/)
- **Work model**: On-site/hybrid at three locations – Irvine, CA (HQ); Ottawa, Canada; and Córdoba, Argentina. Multiple engineering roles (Analog Design, ASIC, DSP, Firmware, Verification) are posted with specific location requirements. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc)
- **Notable perks**: Opportunity to work on next-generation AI infrastructure technology alongside industry pioneers. The company emphasizes building scalable, energy-efficient systems and offers roles across R&D, operations, and manufacturing. [celero.inc](https://celero.inc/careers/)

## Sources
1. [celero.inc](https://celero.inc/) – Company homepage and product description
2. [celero.inc](https://celero.inc/about/) – About page (founding, leadership, mission)
3. [celero.inc](https://celero.inc/celero-communications-secures-140-million-to-accelerate-ai-infrastructure/) – Press release on $140M funding
4. [linkedin.com](https://www.linkedin.com/company/celero-communications) – LinkedIn company page (funding details, headcount, locations, employee breakdown)
5. [greenhouse.io](https://job-boards.greenhouse.io/celerocommunicationsinc) – Careers page (open positions, locations)

## Other roles at Celero Communications, Inc.

- [High-Speed Analog Layout Design Engineer](https://feeny.ai/job/high-speed-analog-layout-design-engineer-celero-communications-inc-cordoba-66dn2b6kaepy) — Córdoba, Argentina
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-jjzw8wst9kw4) — Ottawa, Canada
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-xb3kfd5e3s5y) — San Jose, CA
- [Principal High-Speed Analog Layout Design Engineer](https://feeny.ai/job/principal-high-speed-analog-layout-design-engineer-celero-communications-inc-vahmmaqvrh01) — Irvine, CA
- [IT Help Desk](https://feeny.ai/job/it-help-desk-celero-communications-inc-cordoba-a16t8nfqdwcf) — Córdoba, Argentina
- [ASIC Design Engineer – DSP / Analog / SerDes](https://feeny.ai/job/asic-design-engineer-dsp-analog-serdes-celero-communications-inc-ottawa-pd4fx2w60yhv) — Ottawa, Canada
- [ASIC Design Engineer – DSP / Analog / SerDes](https://feeny.ai/job/asic-design-engineer-dsp-analog-serdes-celero-communications-inc-irvine-we9e7z3fvx1m) — Irvine, CA
- [Principal Product Engineer](https://feeny.ai/job/principal-product-engineer-celero-communications-inc-singapore-derwypn4kenf) — Singapore
- [Principal Analog Design Engineer](https://feeny.ai/job/principal-analog-design-engineer-celero-communications-inc-vancouver-british-sz02fec2vbsc) — Vancouver British Columbia, Canada
- [Principal Analog Design Engineer](https://feeny.ai/job/principal-analog-design-engineer-celero-communications-inc-ottawa-eqcyjq44gc71) — Ottawa, Canada